Wesley W. Terpstra
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431cb41e27
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tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
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2017-03-20 14:49:22 -07:00 |
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Wesley W. Terpstra
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04892fea01
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Monitor: support early ack
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2017-03-20 14:49:19 -07:00 |
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Wesley W. Terpstra
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278f6fea24
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tilelink2: define is{Request,Response} based on spec
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2017-03-20 13:41:02 -07:00 |
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Wesley W. Terpstra
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778e189bba
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Monitor: ProbeAckData and ReleaseData may carry an error
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2017-03-20 11:44:13 -07:00 |
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Wesley W. Terpstra
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48c7aed4e1
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Monitor: any probe supported by the client is legal
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2017-03-20 11:34:19 -07:00 |
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Wesley W. Terpstra
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5a50acfd9d
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Merge pull request #595 from ucb-bar/ignore-tl-c
Ignore TL-C
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2017-03-19 18:49:11 -07:00 |
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Wesley W. Terpstra
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0c92283a61
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rocket icache: tie off b ready
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2017-03-19 17:18:50 -07:00 |
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Wesley W. Terpstra
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c9459fe4eb
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tilelink2 Xbar: don't use unnecessary ports
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2017-03-19 17:02:24 -07:00 |
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Wesley W. Terpstra
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7971947d6c
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tilelink2 Monitor: don't inspect bits if valid is forbidden
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2017-03-19 16:34:23 -07:00 |
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Wesley W. Terpstra
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a4ca424a22
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AHBToTL: finally get the error signal right? (#594)
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2017-03-18 22:24:20 -07:00 |
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Wesley W. Terpstra
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d4272db067
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travis: only run 4 jobs at once (#593)
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
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2017-03-18 04:14:50 -07:00 |
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Wesley W. Terpstra
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f6daa782d3
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AHBToTL: fix the order of updates to d_pause (#592)
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2017-03-17 19:34:40 -07:00 |
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Megan Wachs
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dcc9827ab4
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Rename Prci.scala to Clint.scala (#591)
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
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2017-03-17 15:36:10 -07:00 |
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Wesley W. Terpstra
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db55a1d755
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Fragmenter: fix a bug when underlying device supports larger bursts (#589)
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2017-03-17 11:00:49 -07:00 |
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Wesley W. Terpstra
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eb953c40f0
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Merge pull request #587 from ucb-bar/ahb-fix
ahb: rewrote TLToAHB to avoid retracting requests on stall
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2017-03-16 20:55:39 -07:00 |
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Wesley W. Terpstra
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9b5b3279a6
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AHBToTL: don't report error during idle cycles
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2017-03-16 18:18:29 -07:00 |
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Wesley W. Terpstra
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5efd38bf97
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apb: put both aFlow options under regression
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2017-03-16 15:36:14 -07:00 |
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Wesley W. Terpstra
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882a7ff8ff
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TLToAPB: use the now standard aFlow parameter name
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2017-03-16 15:34:59 -07:00 |
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Wesley W. Terpstra
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e31b84af33
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axi4: use common BufferParams
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2017-03-16 15:32:17 -07:00 |
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Wesley W. Terpstra
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ca2c709d29
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TLBuffer: move TLBufferParams to diplomacy.BufferParams
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2017-03-16 15:19:36 -07:00 |
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Wesley W. Terpstra
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778c8a5c97
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ToAHB: appease AHB VIP
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2017-03-16 15:17:05 -07:00 |
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Wesley W. Terpstra
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963d244094
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unittest: try both aFlow settings of TLToAHB
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2017-03-16 15:13:57 -07:00 |
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Wesley W. Terpstra
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604a164b97
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TLToAHB: rename parameter to aFlow
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2017-03-16 15:10:54 -07:00 |
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Wesley W. Terpstra
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bb49575368
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ahb: rewrote TLToAHB to avoid retracting requests on stall
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2017-03-16 14:36:30 -07:00 |
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Henry Cook
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4f5f686c7e
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bump riscv-tools (#586)
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2017-03-15 18:09:26 -07:00 |
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Wesley W. Terpstra
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625919722c
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Merge pull request #584 from ucb-bar/ahb-in
AHB master port support
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2017-03-14 19:28:09 -07:00 |
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Wesley W. Terpstra
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c95c2ca9c8
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AHB: include bridge unit tests
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2017-03-14 18:34:21 -07:00 |
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Wesley W. Terpstra
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0c5fd76089
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ahb: implement a ToTL bridge
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2017-03-14 18:34:17 -07:00 |
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Wesley W. Terpstra
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7f71df0925
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apb: better test coverage
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2017-03-14 18:34:17 -07:00 |
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Wesley W. Terpstra
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5885bf29b5
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axi4: improve test harness
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2017-03-14 18:34:17 -07:00 |
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Wesley W. Terpstra
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d98fd942f1
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tilelink2: optimize the supportsX check circuits
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2017-03-14 18:34:17 -07:00 |
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Wesley W. Terpstra
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3c5c877409
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tilelink2: make TLBuffer API more flexible
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2017-03-14 14:06:18 -07:00 |
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Wesley W. Terpstra
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6fc3ec3d63
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tileink2: add a TestRAM; a zero-delay RAM useful for testing
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
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2017-03-14 14:06:17 -07:00 |
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Henry Cook
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e9c694522b
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Merge pull request #578 from ucb-bar/priv-1.10
Privileged architecture updates
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2017-03-14 13:20:19 -07:00 |
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Henry Cook
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bb0390630c
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Merge branch 'master' into priv-1.10
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2017-03-13 21:40:12 -07:00 |
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Leway Colin
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1322a02637
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Fixed Hasti can't handle N masters to one slave #571 (#576)
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2017-03-13 20:36:53 -07:00 |
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Henry Cook
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4eb261c895
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Merge pull request #582 from ucb-bar/more-fuzzing
Fuzzer enhancements
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2017-03-13 15:31:51 -07:00 |
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Andrew Waterman
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d6f571cbbb
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Implement mstatus.TSR
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2017-03-13 14:50:06 -07:00 |
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Andrew Waterman
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1fea0460ba
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Support superpage entries in TLB
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2017-03-13 14:50:06 -07:00 |
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Andrew Waterman
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2d267b4940
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Support corner cases in TLBPermissions
Don't crap out if the yes-set or no-set is empty.
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2017-03-13 14:50:06 -07:00 |
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Andrew Waterman
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90b5cc96cb
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Gracefully handle empty ports in AddressDecoder
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2017-03-13 14:50:06 -07:00 |
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Wesley W. Terpstra
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c847559853
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TLB: add a helper API to determine homogeneous page permissions
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2017-03-13 14:50:06 -07:00 |
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Wesley W. Terpstra
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eaf474a081
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LFSR: use random intial value of the start register
We just need to make sure it doesn't initialize randomly stuck at 0.
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2017-03-13 13:17:52 -07:00 |
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Henry Cook
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fe287864ef
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bump firrtl
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2017-03-13 13:14:16 -07:00 |
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Henry Cook
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1a3fec61c0
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Merge branch 'master' into priv-1.10
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2017-03-13 11:59:18 -07:00 |
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Wesley W. Terpstra
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d2da33e4b1
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Fuzzer: use different LFSR seeds based on simulator seed
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2017-03-11 02:53:43 -08:00 |
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Wesley W. Terpstra
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bb6108abd5
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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Wesley W. Terpstra
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0c7fb87390
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TLDelayer: insert noise on invalid cycles
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2017-03-11 02:53:43 -08:00 |
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Jacob Chang
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1c6dde8c15
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Make parameters for TLToAHB and TLToAXI4 accessable (#581)
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2017-03-10 22:26:38 -08:00 |
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Henry Cook
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dbc8f4b30b
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last => done
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2017-03-10 15:58:38 -08:00 |
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