Wesley W. Terpstra
fef5054cec
diplomacy: disambiguate names only when necessary
...
If two (or more) 'auto_' things have the same name, append _0 and _1 to them.
The order of definitions is unaffected; ie:
a => a_0
b => b_0
b => b_1
c => c
a => a_1
2017-09-25 16:12:34 -07:00
pbing
a86a9c5564
Fix omitted parameter ( #1014 )
2017-09-25 14:11:28 -07:00
Wesley W. Terpstra
5323cf88dd
util: add Option.unzip
2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3
diplomacy: eliminate some wasted IdentityNodes using cross-module refs
2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
bc225a4e82
diplomacy: place Monitors inside LazyModules sinks
...
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.
Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
2017-09-22 23:36:17 -07:00
Wesley W. Terpstra
cfb7f13408
diplomacy: capture SourceInfo at point of := in Edge parameters
2017-09-22 22:25:56 -07:00
Wesley W. Terpstra
16969eb1f6
diplomacy: spelling fix
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
53f6999ea8
Splitter: reuse TLCustom node instead of special diplomacy case
2017-09-22 14:58:39 -07:00
Wesley W. Terpstra
6fa5250e1f
config: fix warning
2017-09-22 14:58:36 -07:00
Wesley W. Terpstra
17ba209ed0
coreplex: name LazyModules
2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
1fedabcb55
tilelink: invoke LazyModule() at point of monitor binding
2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
dfc815f4d3
rocket: invoke LazyModule at point of use/binding
2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
87d597c70d
ahb apb: remove unintentional var
2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
d89ee9d9d4
nodes: grab a name on construction
2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
3656e975a1
diplomacy: ValName captures val bindings for Nodes
2017-09-22 14:38:47 -07:00
Henry Cook
5662d1de0b
Merge pull request #1012 from freechipsproject/halt-and-catch-fire
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Halt and Catch Fire
2017-09-22 09:30:30 -07:00
Henry Cook
81e136aa37
rocket: give l2 tlb a nice name
2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517
Revert "try to give seqmems clearer names"
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This reverts commit 8db5bbbae0
2017-09-21 18:02:32 -07:00
Henry Cook
e0b9f9213a
make halt_and_catch_fire Optional
2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721
tile: add halt_and_catch_fire signal
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for unrecoverable / fatal errors
2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615
rocket: base trait for reporting ecc errors
2017-09-21 14:58:47 -07:00
Megan Wachs
ffa3ab29ac
Merge pull request #1006 from freechipsproject/async_reset_reg
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async_reset_reg: Don't randomize the register if rst is asserted anyway
2017-09-21 11:48:04 -07:00
Jim Lawson
4f58aab26f
Bumpplugins - add sbt-coverage ( #1004 )
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Don't advance to plugin versions that are incompatible with current chisel3 code.
2017-09-20 17:17:55 -07:00
Andrew Waterman
88c782cc70
Report D$ uncorrectable errors on C channel
2017-09-20 17:15:11 -07:00
Andrew Waterman
6bc20942b5
Don't cache TL error responses; report access exceptions
2017-09-20 17:01:08 -07:00
Henry Cook
323a207bdd
Merge pull request #1005 from freechipsproject/trace
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Rename trace.addr -> iaddr
2017-09-20 15:34:45 -07:00
Andrew Waterman
9b828a2640
Only look at error signal on last beat
2017-09-20 15:15:21 -07:00
Megan Wachs
cda89fbacb
async_reset_reg: Don't randomize the register if rst is asserted anyway
2017-09-20 14:47:00 -07:00
Andrew Waterman
026fa14bf8
Rename trace.addr -> iaddr
2017-09-20 14:32:41 -07:00
Henry Cook
1cb91eed41
Merge pull request #1003 from freechipsproject/ma-fetch
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Don't write badaddr on misaligned fetch exceptions
2017-09-20 14:28:26 -07:00
Andrew Waterman
5b2f458214
Merge branch 'master' into ma-fetch
2017-09-20 12:18:03 -07:00
Andrew Waterman
f1a506476b
Merge pull request #994 from freechipsproject/beu
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Add L1 bus-error unit
2017-09-20 12:17:08 -07:00
Henry Cook
00cf089350
Merge pull request #1002 from freechipsproject/trace
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Add instruction-trace port
2017-09-20 11:50:40 -07:00
Andrew Waterman
f5bd639863
Don't write badaddr on misaligned fetch exceptions
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It's optional, and we were doing it wrong before, so just don't do it.
2017-09-20 10:52:41 -07:00
Andrew Waterman
db57e943f3
Report TL errors into D$
2017-09-20 00:05:07 -07:00
Andrew Waterman
aaad73f019
Add an intra-tile xbar
2017-09-20 00:05:07 -07:00
Andrew Waterman
afad25fceb
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
Andrew Waterman
dbf599f6a1
Support SynchronizerShiftReg(sync = 0)
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This makes it easier to parameterize code where the synchronizer
might not always be needed.
2017-09-20 00:05:07 -07:00
Andrew Waterman
79dab487fc
Implement bus error unit
2017-09-20 00:05:07 -07:00
Andrew Waterman
ed18acaae0
Report D$ errors
2017-09-20 00:05:07 -07:00
Andrew Waterman
034ea722f4
Report I$ errors
2017-09-20 00:05:07 -07:00
Andrew Waterman
9a175b0fb1
Statically report error correction/detection capability from ECC codes
2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641
Add instruction-trace port
2017-09-19 22:59:57 -07:00
Andrew Waterman
acea94bcef
Merge pull request #1001 from freechipsproject/address-decoder
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Address decoder "improvements"
2017-09-19 22:38:53 -07:00
Jacob Chang
b4fc5104d4
Add cover property API that can be refined through Config PropertyLibrary ( #998 )
2017-09-19 19:26:54 -07:00
Henry Cook
57e8fe0a6b
Merge pull request #1000 from freechipsproject/name-seqmems
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try to give seqmems clearer names for use with external tools
2017-09-19 17:59:00 -07:00
Andrew Waterman
87b92cb206
Scan AddressDecoder bits left to right
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This heuristic is brittle but fixes deduplication in RocketTile.
2017-09-19 17:47:24 -07:00
Andrew Waterman
72bd89a2af
Add another AddressDecoder debug message
2017-09-19 17:47:17 -07:00
