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1e0aca7358
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dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455)
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2016-11-25 15:26:22 -08:00 |
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38c5af5bad
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[rocket] cleanup mshr logic
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2016-11-23 12:09:56 -08:00 |
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dae6772624
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factor out common cache subcomponents into uncore.util
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2016-11-23 12:09:35 -08:00 |
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c65c255815
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[coreplex] TileId moved to groundtest
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2016-11-23 12:08:45 -08:00 |
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5f3fb64ef0
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Per ABI, only x1 and x5 should be treated as function returns
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
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2016-11-22 12:01:05 -08:00 |
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5fe107bb07
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rocket: pass scratchpad address to block dcache
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2016-11-21 21:13:26 -08:00 |
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c18bc07bbc
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TLB: determine RWX from TL2 properties directly
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2016-11-21 21:13:26 -08:00 |
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28c6be90ab
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[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
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2016-11-20 19:36:51 -08:00 |
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ff9b5bf8fc
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[rocket] nbdcache release bugfix
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2016-11-20 19:07:06 -08:00 |
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3f47d5b5eb
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[rocket] re-enable working NBDcache (passes Tracegen)
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2016-11-19 19:19:16 -08:00 |
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9dd12545d0
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[Rocket] Send correct type for iomshr reqs
Also contain grow param bugfix
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2016-11-19 19:04:06 -08:00 |
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32a1c27441
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rocket: disable nbdcache until it's fully ported
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2016-11-18 19:55:24 -08:00 |
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452bb2fc80
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dcache fix TinyConfig
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2016-11-18 19:50:34 -08:00 |
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2976fd84e4
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[rocket] resolve cde/config conflicts
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2016-11-18 19:11:34 -08:00 |
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8b908465e0
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[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
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2016-11-18 19:04:06 -08:00 |
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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30425d1665
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rocketchip: eliminate all Knobs
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2016-11-18 14:31:42 -08:00 |
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5bd343bac8
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[rocket] d_last && d.fire() => d_done
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2016-11-17 18:42:59 -08:00 |
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1ddccb1b33
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[rocket] add TODO for single cycle ack
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2016-11-17 18:42:59 -08:00 |
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e1992d7c55
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[rocket] grant addr bugfix
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2016-11-16 18:12:06 -08:00 |
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da7ecfd189
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[rocket] probeack vs probeackdata bugfix
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2016-11-16 17:27:02 -08:00 |
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1f51564577
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[rocket] dcache probe ack data bugfix
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2016-11-16 14:25:21 -08:00 |
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66a2c5544e
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[rocket] L1D acquire addr bugfix
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2016-11-16 13:38:52 -08:00 |
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c5e03c9c76
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[rocket] dcache release addr bugfix
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2016-11-16 13:14:51 -08:00 |
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10e459fedb
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rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
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2016-11-15 18:27:52 -08:00 |
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0e30364f56
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WIP
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2016-11-14 13:39:01 -08:00 |
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c0efd247b0
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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b7730d66f2
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WIP bugfixes: run until corrupted WB data (beats repeated)
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2016-11-11 18:34:48 -08:00 |
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71315d5cf5
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WIP scala compile and firrtl elaborate; monitor error
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2016-11-11 13:07:45 -08:00 |
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afa1a6d549
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WIP uncore and rocket changes compile
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2016-11-10 15:57:29 -08:00 |
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92ee498521
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rocket scratchpad: support atomics
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2016-10-31 11:42:47 -07:00 |
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0cc00e7616
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regressions: test scratchpad
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2016-10-31 11:42:47 -07:00 |
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545154c1c3
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groundtest: make it happy with TL2 addressing
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2016-10-31 11:42:47 -07:00 |
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e9725aea2f
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rocketchip: all of the address map now comes from TL2
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2016-10-31 11:42:44 -07:00 |
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b68bc449e7
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rocket: put a Fragmenter infront of the scratchpad
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2016-10-31 11:42:13 -07:00 |
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825c253a72
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rocketchip: move TL2 and cake pattern into Coreplex
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2016-10-31 11:42:13 -07:00 |
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11121b6f4c
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rocket: convert scratchpad to TL2
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2016-10-31 11:42:13 -07:00 |
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dddb50a942
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BuildTiles: convert to LazyTile
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2016-10-31 11:42:13 -07:00 |
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85f3788ab5
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initialize s2_hit to solve #401
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2016-10-21 14:53:55 -07:00 |
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c22438b822
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Fix an overly strict D$ assertion
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2016-10-06 15:52:46 -07:00 |
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5980dc160f
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Don't allow multiple entries for same PC in BTB
Necessary for RVC forward-progress guarantee.
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2016-10-06 11:30:45 -07:00 |
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eddf1679f5
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Use <> instead of := for bi-directional connections
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2016-10-04 22:29:39 -07:00 |
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67593fdf2d
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Explicitly zap some S-mode CSRs when not using S-mode
|
2016-10-04 22:29:39 -07:00 |
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064c9ebdc6
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Don't report I$ fetch faults on TLB misses!
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2016-10-04 14:37:25 -07:00 |
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516481b68b
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Improve back-to-back integer multiplication performance
More exact hazard checking in the decode stage avoids a pipeline flush.
|
2016-10-04 14:37:25 -07:00 |
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7b69f1f261
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Don't enter D$ flush state machine if grant outstanding
|
2016-10-04 14:37:25 -07:00 |
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28beb33943
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Make any intervening load/store/fence fail an LR/SC sequence
This catches LR/SC misuses more quickly.
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2016-10-04 14:37:25 -07:00 |
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e0188f8aa4
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Don't implicitly fence on CSR instructions
CSRs that have an effect on I/O should use an explicit FENCE.
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2016-10-01 19:44:10 -07:00 |
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b772edcb1b
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Allow hit-under-MMIO and multiple MMIOs in blocking D$
The latter feature is by default disabled, since there aren't enough
ID bits.
|
2016-10-01 19:44:05 -07:00 |
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ab3219cf6e
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don't use Scala to Chisel implicit conversions outside of rocket
|
2016-09-29 14:35:42 -07:00 |
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