Andrew Waterman
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Andrew Waterman
dc662f28a0
Specify width on s1_pc to avoid width inference problem
2016-04-01 17:28:42 -07:00
Andrew Waterman
4480d1e817
Don't compile BTB when nEntries=0
2016-04-01 15:14:45 -07:00
Andrew Waterman
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
...
separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
Christopher Celio
f526d380fd
separate btb response mask from the frontend mask
...
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
120361226d
fix more Chisel3 deprecations
2016-01-14 14:46:31 -08:00
Howard Mao
13ce91e453
fix Chisel3 compat warnings in ICache and FPU
2016-01-12 12:43:48 -08:00
Howard Mao
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
Colin Schmidt
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
