riscv/rocket-chip
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2116 Commits

Author SHA1 Message Date
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls () 
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
 2017-11-08 15:31:19 -08:00
Andrew Waterman
4514adb77c
Merge pull request from freechipsproject/local-error-interrupt 
generate local interrupts on bus/ecc errors
 2017-11-07 14:19:53 -08:00
Henry Cook
d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles () 2017-11-07 13:47:56 -08:00
Andrew Waterman
34f38b0fb1 Don't permit vectoring of high interrupts 
Send them to the base of the vector to obviate an adder
 2017-11-07 01:59:30 -08:00
Andrew Waterman
6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts 2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187 Generate local interrupt on bus errors 
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
 2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7 Make BusErrorUnit support 32-bit stores 
Otherwise it isn't too useful for RV32!
 2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt 2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request from freechipsproject/aswaterman-patch-1 
Don't emit PTW covers when !usingVM
 2017-11-06 18:03:36 -08:00
Andrew Waterman
95d00b13cc Report ITIM slave port errors to BusErrorUnit 2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6 Report ITIM uncorrectable errors over D-channel 2017-11-06 12:32:45 -08:00
Wesley W. Terpstra
7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test 2017-11-06 12:05:44 -08:00
Wesley W. Terpstra
88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns 2017-11-06 11:53:09 -08:00
Wesley W. Terpstra
25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error 2017-11-06 11:31:23 -08:00
Wesley W. Terpstra
dcf67b49fa
BusBypass: only stall A once the last beat is accepted () 
When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
 2017-11-06 11:13:15 -08:00
Andrew Waterman
f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Andrew Waterman
7bef935d2a
Don't emit PTW covers when !usingVM 2017-11-03 15:03:27 -07:00
Wesley W. Terpstra
16116991e7
Fix stateless caching () 
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
 2017-11-01 11:05:56 -07:00
Wesley W. Terpstra
4ccdbecb63
Async covers () 
* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic
 2017-11-01 11:03:45 -07:00
Wesley W. Terpstra
84145959e1
tilelink: fix error fragmentation from multibeat to multibeat () 
Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
 2017-10-31 17:34:46 -07:00
Wesley W. Terpstra
8ec06151b0
interrupts: Crossing should use asynchronously reset registers () 
Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
 2017-10-31 16:29:06 -07:00
Megan Wachs
f86489b59e
JTAG: Use sorted map for stability () 
* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup
 2017-10-31 15:33:41 -07:00
Andrew Waterman
3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM () 
Workaround: disable interrupts and then do:

.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
 2017-10-31 00:49:56 -07:00
Wesley W. Terpstra
45a904b396 ahb: ignore hrdata on an AHB error 
From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
6318d7d44c ahb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
2912a76a2b axi4: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
e8ed450f13 unit tests: do not use LFSR16 which has a common seed! 
We want each LFSR to generate independent noise.
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
ec70e5fb02 apb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0280a1f218 tilelink: add the ErrorEvaluator, a test bench error helper 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
d6f1612812 tilelink: ToAHB should make read errors sticky as well 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0992a459be tilelink: Fragmenter should combine errors 2017-10-30 21:09:42 -07:00
Wesley W. Terpstra
13d0bf6808 tilelink: Monitor now enforces spec-defined error rules 2017-10-30 11:27:07 -07:00
Wesley W. Terpstra
a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
6aac658184 diplomacy: convert all helper objects to return nodes 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra
eeb11a2693 coreplex: eliminate dead code 2017-10-27 01:13:35 -07:00
Wesley W. Terpstra
9f83db998e tile: don't chain too many unneeded TileLink adapters () 2017-10-27 01:12:58 -07:00
Wesley W. Terpstra
e12bdfdf9b coreplex: attach example external interrupts () 
Fixes
2017-10-27 01:12:42 -07:00
Wesley W. Terpstra
13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul () 2017-10-26 23:39:56 -07:00
Wesley W. Terpstra
1d8e539362 coreplex: confirm crossings actually cross the right boundary 2017-10-26 15:53:01 -07:00
Wesley W. Terpstra
60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope 2017-10-26 15:19:05 -07:00
Wesley W. Terpstra
a060c37173 diplomacy: expose the API to query a Node for its neighbours 2017-10-26 15:08:06 -07:00
Wesley W. Terpstra
e2d6d4d725 diplomacy: eliminate bindings dead-code 2017-10-26 15:02:21 -07:00
Wesley W. Terpstra
9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml 2017-10-26 13:58:52 -07:00