Yunsup Lee
a4c1942958
flatten Coreplex module hierarchy
2016-09-02 17:45:08 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Andrew Waterman
fb50f7c9dd
Set default TileLink width to XLen
2016-09-02 15:27:54 -07:00
Andrew Waterman
6872000f5e
Merge pull request #239 from ucb-bar/move_rtc
...
Move RTC
2016-09-02 15:17:49 -07:00
Megan Wachs
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Andrew Waterman
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
Andrew Waterman
8dbee2b133
Don't conditionalize running bmarks on UseVM
2016-08-29 13:43:29 -07:00
Andrew Waterman
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
Andrew Waterman
9ca82dd397
reset default MulDiv config to moderately fast default
...
Closes #228 .
In commit 3f8c60bbd6
2016-08-29 12:31:52 -07:00
Henry Cook
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
mwachs5
22ffe36258
Add a queue for timing QoR between L2->MMIO network ( #217 )
2016-08-19 22:51:49 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
