Wesley W. Terpstra
c82b371354
rocketchip: remove obsolete TL1 config
2016-11-17 14:24:45 -08:00
Wesley W. Terpstra
dfc3a0dafb
tilelink2: do not depend on obsolete TL1 configuration
2016-11-17 14:07:53 -08:00
Wesley W. Terpstra
8a0ecdaaad
groundtest: ComparatorConfig lives again
2016-11-17 11:07:49 -08:00
Henry Cook
92e233d596
[groundtest] testramaddr constant in package
2016-11-16 18:42:56 -08:00
Henry Cook
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
Henry Cook
84f249bd03
[rocketchip] BigInt cast
2016-11-16 18:11:06 -08:00
Henry Cook
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
Henry Cook
75d4347192
[groundtest] runs tests with new coreplex and top
2016-11-16 17:05:53 -08:00
Henry Cook
24e3216fcf
coreplex: allow zero interrupt sink/sources
2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03
tilelink2 Broadcast: improve bufferless throughput
2016-11-16 16:50:36 -08:00
Henry Cook
408e78e35e
rocketchip Periphery: ExtMem and ExtBus Configs
2016-11-16 16:50:30 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
Richard Xia
81d98304dc
Merge pull request #438 from ucb-bar/bump-riscv-tools-for-riscv-test-updates
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Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization feature.
2016-11-16 12:26:48 -08:00
Wesley W. Terpstra
06a7b95d0d
tilelink2 broadcast: support bufferless Config
2016-11-16 12:25:11 -08:00
Wesley W. Terpstra
3703ed39f7
groundtest: PTW needs atomics
2016-11-16 12:16:54 -08:00
Wesley W. Terpstra
5d2e637a4a
tilelink2 Legacy: uncached TL never needs manager_xact_id
2016-11-16 12:16:25 -08:00
Richard Xia
6e5dd45f9a
Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization fix.
2016-11-16 11:33:15 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Henry Cook
2d68f12115
[tl2] give groundtest tile some output nodes
2016-11-14 18:09:40 -08:00
Wesley W. Terpstra
ab3dafb8bc
Monitor: restore Probe&Acquire checks
2016-11-14 15:36:52 -08:00
Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
32fd11935c
rocketchip: use TL2 and AXI4 for memory subsytem
2016-11-04 13:36:47 -07:00
Wesley W. Terpstra
9d77e34bee
tilelink2 Filter: make transfer cap robust against large filters
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
4a2cf6431b
coreplex: make 'mem' port an Option until we can use a Seq
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
8f757a9135
coreplex: rename BankedL2 trait to BankedL2CoherenceManagers
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b
tilelink2 Broadcast: support "bufferless" implementation
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4
tilelink2 Broadcast: only support caching readable devices
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
d03046d11c
coreplex: fix BankedL2 line width
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
ea602790a8
Merge pull request #432 from ucb-bar/tl2-address-filtering
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Tl2 address filtering
2016-11-04 00:12:43 -07:00
Wesley W. Terpstra
da3cc3b299
coreplex: TileLink2 l1tol2 memory channels
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
0f3947bb86
tilelink2 Broadcast: add special case handling for 0 cached clients
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb
tilelink2: Filter adapter removes some of the address space
2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
163b7577bd
Merge pull request #431 from ucb-bar/tl2-broadcast
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Tl2 broadcast
2016-11-03 15:39:43 -07:00
Wesley W. Terpstra
86ba94781b
tilelink2: broadcast coherence manager
2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d
tilelink2 Parameters: sinkId is per port, not per manager
2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
1b016051e8
Merge pull request #424 from ucb-bar/coreplex-cake
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Coreplex cake
2016-10-31 16:49:27 -07:00
Wesley W. Terpstra
ed4224dde4
tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull
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If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
f83d1d0aaf
coreplex: rename trait CoreplexRISCVPlatform
...
This makes it clear we are talking about the devices one expects in the
platform, not the ISA.
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
f943c5d6ef
rocketchip: connect rtcTick to coreplex
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
4a0b29850c
coreplex: reattach clint interrupt
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
a12fea51e8
Plic: skip reserved interrupt in interrupt map printout
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
aabd17d935
rocketchip: must create bundles within Module scope
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1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs
Solution: pass a bundle constructor to the cake base class
Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.
Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
