Wesley W. Terpstra
f0ffb7e31e
tilelink: initialize toggle in Fragmenter ( #894 )
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No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
2017-07-26 10:21:31 -07:00
Andrew Waterman
27d5557177
Merge pull request #891 from freechipsproject/fix-l2-tlb
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Fix L2 TLB
2017-07-26 09:43:16 -07:00
Andrew Waterman
5a5b78b15e
Improve L2 TLB coding style
2017-07-26 02:22:43 -07:00
Andrew Waterman
5a9c673f41
Fix L2 TLB response bug
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Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
2017-07-26 02:20:41 -07:00
Andrew Waterman
acca0fccf5
Fix BTB not being refilled on some indirect jumps
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We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB. That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to. This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow. Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.
This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b
Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend
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Acquire before release; jump in frontend
2017-07-25 16:26:47 -07:00
Wesley W. Terpstra
c2b8b08461
tilelink: fix Fragmenter source re-use bug ( #888 )
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Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.
However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.
To solve this, we alternate an a.source bit every time D completes a txn.
2017-07-25 16:23:55 -07:00
Andrew Waterman
15878d4691
Perform some control-flow transfers within the Frontend
2017-07-25 15:19:16 -07:00
Andrew Waterman
62c4080585
Add RVC instruction patterns
2017-07-25 15:19:16 -07:00
Andrew Waterman
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
Andrew Waterman
86ccd935fc
Add method to print perf events
2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
Andrew Waterman
3ced04b70a
Mix in trait to connect global_reset_vector
2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb
TLFragmenter: Continuing my spot battles on requires without explanatory strings ( #882 )
2017-07-21 21:55:32 -07:00
Yunsup Lee
cf75c2049d
Merge pull request #878 from freechipsproject/fix-fifofixer
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tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 20:22:16 -07:00
Yunsup Lee
21954c1c73
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 19:38:27 -07:00
Howard Mao
4d784ad693
add cloneType to RegisterWriteIO and RegisterReadIO ( #874 )
2017-07-18 18:52:31 -07:00
Wesley W. Terpstra
8d793daf9c
Merge pull request #876 from freechipsproject/sq-helper
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ShiftQueue: support constant propagation
2017-07-18 16:30:23 -07:00
Wesley W. Terpstra
a9c58e9d9f
diplomacy: support creating ShiftQueues as well
2017-07-18 14:57:02 -07:00
Wesley W. Terpstra
c0a3bb58e9
ShiftQueue: use Vec of Bool to support constant prop of enq.valid
2017-07-18 14:56:59 -07:00
Colin Schmidt
6d0821f19a
Update readme to reflect config name changes ( #871 )
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also update list of files expected to be seen in generated-src
2017-07-18 07:27:03 -07:00
Wesley W. Terpstra
416629b3bf
tilelink: FIFOFixer should fix no domain => domain cases ( #873 )
2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
d09a985729
zero: fix attachment in multichannel case ( #870 )
2017-07-17 21:48:31 -07:00
Wesley W. Terpstra
fc75ada577
tilelink: Monitor should report line numbers of connection that failed ( #872 )
2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784
fix the TLFuzzer IO ( #869 )
2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144
tilelink: it is now legal to have errors on {Release,Hint}Ack ( #864 )
2017-07-14 16:13:30 -07:00
Richard Xia
9ade7af013
Merge pull request #862 from freechipsproject/plic-max-pri-dts
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PLIC: Add maxPri as well as ndev in DTS
2017-07-13 17:08:21 -07:00
Richard Xia
f0481801df
Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts
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Rename offchip-interrupts to external-interrupts.
2017-07-13 16:52:57 -07:00
Megan Wachs
35464782b5
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
Richard Xia
d62787357b
Rename offchip-interrupts to external-interrupts.
2017-07-13 15:56:22 -07:00
Shreesha Srinath
f2533ce825
bootrom: Adding bootrom parameters ( #857 )
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BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
2017-07-13 13:40:02 -07:00
Megan Wachs
f646bed3ea
PLIC: Use longer DTS name for Max Priorities.
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I used the singular because there is really only one max priority
2017-07-13 13:37:22 -07:00
Megan Wachs
0800fd3ed9
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 13:18:50 -07:00
Wesley W. Terpstra
b7f1ba3428
tilelink: FIFOFixer must support null cases ( #860 )
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In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
2017-07-12 22:20:31 -07:00
Wesley W. Terpstra
0053a060ae
Merge pull request #859 from freechipsproject/fifo-fixer-configable
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Fifo fixer configable
2017-07-12 19:44:23 -07:00
Wesley W. Terpstra
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
Wesley W. Terpstra
09b9d33a9a
tilelink: FIFOFixer now has a policy parameter
2017-07-12 17:38:55 -07:00
Wesley W. Terpstra
b363a94480
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
Wesley W. Terpstra
c8a7648169
diplomacy: only evaluate a Nexus node's map function once
2017-07-12 16:20:55 -07:00
Wesley W. Terpstra
af3976aa67
regmapper: add byte-sized RegField helper function ( #854 )
2017-07-10 21:08:02 -07:00
Megan Wachs
177ccbb663
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was ( #855 )
2017-07-10 21:07:50 -07:00
Jim Lawson
287219da06
Merge pull request #851 from freechipsproject/chisel3clock
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Use chisel3 Clock() method.
2017-07-10 08:33:46 -07:00
Wesley W. Terpstra
29f5f77817
Merge pull request #853 from freechipsproject/sram-errors
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SRAM errors
2017-07-07 22:44:28 -07:00
Wesley W. Terpstra
5db0e770d5
tilelink: TestSRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
702143eb33
tilelink: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
