riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
113 Commits 1 Branch 0 Tags
9e6b86fe85c60f0f275ca28c157562bc84cffff7
Commit Graph
12 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman d59bddfbf1 fix I$ miss replay bug 2012-01-21 20:42:13 -08:00
Andrew Waterman 07f184df2f adhere to new chisel c naming convention 2012-01-18 15:23:21 -08:00
Andrew Waterman e4cf6391d7 fix i$ miss pathology and badvaddr bug 2012-01-17 23:47:35 -08:00
Andrew Waterman 0369b05deb move replays to writeback stage 2012-01-17 21:12:31 -08:00
Andrew Waterman 1c8f496811 fix fpga build 2012-01-13 20:04:11 -08:00
Andrew Waterman acf3134e80 minor control logic cleanup 2012-01-12 14:19:18 -08:00
Andrew Waterman 4807d7222b use replay to handle I$ misses 
this eliminates a long path in the fetch stage
 2012-01-11 19:20:20 -08:00
Andrew Waterman 1a7bfd4350 remove icache req_rdy signal 2012-01-11 18:27:11 -08:00
Andrew Waterman bcb55e581a remove host.start signal, use reset instead 2012-01-11 17:49:32 -08:00
Andrew Waterman 92dda102b6 slight control logic cleanup 2012-01-11 16:56:40 -08:00
Andrew Waterman 938b142d64 require writes to memory to be uninterrupted 2012-01-03 18:41:53 -08:00
Andrew Waterman 142dfc6e07 made tohost/fromhost 64 bits wide 2012-01-03 15:09:08 -08:00