Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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fbd44ea936
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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6664af3bc0
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cleanup before adding dtlb
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2011-11-09 23:27:29 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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7479e085ec
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 22:04:45 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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