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Author SHA1 Message Date
Wesley W. Terpstra
6ec2e7c5bd tilelink2: Legacy should preserve the access size (#378) 
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
 2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
72e8c6f589 Merge pull request #379 from ucb-bar/axi-prefactor 
Axi prefactor
 2016-10-03 16:49:37 -07:00
Wesley W. Terpstra
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303 tilelink2: Nodes should accept full PortParameters 
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
 2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf graphML: CTO's like colour 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084 LazyModule: output final verilog Module name 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
Yunsup Lee
5ff3d3d61c correctly initialize with seed 2016-10-02 17:31:32 -07:00
Wesley W. Terpstra
52c1a053ff tilelink2 RegisterRouter: test fully Decoupled behaviour 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4 tilelink2 RegisterCrossing: Queues go from RV to Irrevocable 
AsyncQueue is still a Queue.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530 RegMapper: clarify interface is DecoupledIO 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad tilelink2 RegField: clarify restrictions on functions 
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428 tilelink2 RegisterRouter: fix output data glitches 
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
 2016-10-02 02:24:02 -07:00
Andrew Waterman
e0188f8aa4 Don't implicitly fence on CSR instructions 
CSRs that have an effect on I/O should use an explicit FENCE.
 2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b Allow hit-under-MMIO and multiple MMIOs in blocking D$ 
The latter feature is by default disabled, since there aren't enough
ID bits.
 2016-10-01 19:44:05 -07:00
mwachs5
784f0cf0b6 Merge pull request #370 from ucb-bar/move_clint_and_plic 
clint & plic: Move the default addresses
 2016-10-01 16:18:54 -07:00
Megan Wachs
28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a tilelink2 Isolation: add enable signal (#368) 2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
891a253bee Merge pull request #367 from ucb-bar/tl2-isolation 
Tl2 isolation
 2016-09-30 02:19:44 -07:00
Wesley W. Terpstra
d3547a6193 tilelink2: Isolation gate insertion module 2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52 tilelink2 Crossing: helpful constructor objects 2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3 tilelink2: helper objects operate on OutwardNodes 2016-09-30 01:39:35 -07:00
Howard Mao
a1fa0733e5 Merge pull request #366 from ucb-bar/slowio-change 
Change the configuration interface of SlowIO
 2016-09-29 23:19:53 -07:00
Howard Mao
4b86802b1a change the configuration interface of SlowIO 2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
8730887baa Merge pull request #364 from ucb-bar/tl2-async-nodes 
Tl2 async nodes
 2016-09-29 18:18:31 -07:00
Wesley W. Terpstra
6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains 2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c tilelink2: add types for a TL clockless interface 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831 tilelink2: rename BaseNode to SimpleNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves 
This lets us create nodes which transform from one bus to another.
 2016-09-29 17:33:11 -07:00
Howard Mao
ceb9c53c7d Merge pull request #360 from ucb-bar/move-to-util 
Move a bunch more things into util package
 2016-09-29 15:59:46 -07:00
Andrew Waterman
2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce Default mtvec=0, not None 
Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
 2016-09-29 13:52:41 -07:00
Megan Wachs
1e43512142 jtag: Actually apply the sticky bits 2016-09-29 13:49:34 -07:00
Megan Wachs
a4b81aebe0 jtag: Apply sticky bits for error and busy according to the current Debug Spec 2016-09-29 13:49:26 -07:00
Megan Wachs
fc4d6ed0c6 jtag: clean up debug flags in regression/Makefile 2016-09-29 13:49:21 -07:00
Megan Wachs
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
Colin Schmidt
4ac0ef2940 bump torture pointer after sim name change 2016-09-29 10:45:06 -07:00
Henry Cook
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry Cook
32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9 [tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356) 2016-09-27 18:06:21 -07:00