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Commit Graph

509 Commits

Author SHA1 Message Date
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
ca5f98f138 tilelink2: Hints are not special
Hints have a TransferSize limit just like all other message types.
2016-09-12 17:15:28 -07:00
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer
Multiple bug-fixes and actual source id generation.
2016-09-12 17:00:58 -07:00
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials
this will require a larger address refactoring TBD
2016-09-12 17:00:50 -07:00
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
82681179cb [tilelink2] Edges: add size to addr_lo.
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
2016-09-12 16:58:09 -07:00
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
656aa78f7d Pipeline FMAs more deeply by default
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
eaa4b04ee5 Check D$ store->load collisions more precisely
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
We can more reliably find the current LazyModule from the LazyModule.stack
2016-09-08 23:06:59 -07:00
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
2016-09-08 21:34:20 -07:00
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00
cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
9bfd8c1cf5 TL2 WidthWidget (#258)
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
2016-09-08 10:38:38 -07:00
e35e7b2ee3 Fix routing in non-contiguous MMIO regions
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
02a2439222 Support a degenerate PLIC with no interrupts
Resolves #249
2016-09-07 11:21:13 -07:00
70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
a7f47f3c23 Reduce default BTB size
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
2016-09-07 01:51:27 -07:00
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00