972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
03f2fe02ac
coreplex: support rational crossing to L2 ( #534 )
2017-01-27 17:09:43 -08:00
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
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PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
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* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
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This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
915697cb09
Fix FEQ flag generation ( #479 )
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FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
36fe024671
CacheName no longer needed in RoCCInterface
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With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
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We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
c18bc07bbc
TLB: determine RWX from TL2 properties directly
2016-11-21 21:13:26 -08:00
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
ff9b5bf8fc
[rocket] nbdcache release bugfix
2016-11-20 19:07:06 -08:00
3f47d5b5eb
[rocket] re-enable working NBDcache (passes Tracegen)
2016-11-19 19:19:16 -08:00
9dd12545d0
[Rocket] Send correct type for iomshr reqs
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Also contain grow param bugfix
2016-11-19 19:04:06 -08:00
32a1c27441
rocket: disable nbdcache until it's fully ported
2016-11-18 19:55:24 -08:00
452bb2fc80
dcache fix TinyConfig
2016-11-18 19:50:34 -08:00
2976fd84e4
[rocket] resolve cde/config conflicts
2016-11-18 19:11:34 -08:00
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
10e459fedb
rocket: change connection between rocketchip and coreplex
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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
b68bc449e7
rocket: put a Fragmenter infront of the scratchpad
2016-10-31 11:42:13 -07:00
