Andrew Waterman
|
2786e42d99
|
Don't register interrupts in CSRFile
They are usually registered outside the tile in a CDC.
|
2017-10-03 17:34:18 -07:00 |
|
Andrew Waterman
|
5cfe070932
|
Add option to make misa read-only
|
2017-10-03 17:34:18 -07:00 |
|
Andrew Waterman
|
09468a272b
|
Add option to remove basic counters (mcycle/minstret)
|
2017-10-03 17:34:18 -07:00 |
|
Andrew Waterman
|
ab0821f25b
|
Move microarchitecture-neutral params from Rocket to Core
This makes some of the units more reusable.
|
2017-10-03 17:34:18 -07:00 |
|
Andrew Waterman
|
190d5c50d9
|
Remove deprecated custom-CSR support
|
2017-10-03 17:34:18 -07:00 |
|
Andrew Waterman
|
78f3877e02
|
Trace tval field should be zero when not taking exceptions
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2017-09-27 12:51:10 -07:00 |
|
Andrew Waterman
|
583adeee88
|
Separate interrupt bit from cause field in trace bundle
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2017-09-27 12:41:30 -07:00 |
|
Andrew Waterman
|
026fa14bf8
|
Rename trace.addr -> iaddr
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2017-09-20 14:32:41 -07:00 |
|
Andrew Waterman
|
5b2f458214
|
Merge branch 'master' into ma-fetch
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2017-09-20 12:18:03 -07:00 |
|
Andrew Waterman
|
f5bd639863
|
Don't write badaddr on misaligned fetch exceptions
It's optional, and we were doing it wrong before, so just don't do it.
|
2017-09-20 10:52:41 -07:00 |
|
Andrew Waterman
|
4d6d6ff641
|
Add instruction-trace port
|
2017-09-19 22:59:57 -07:00 |
|
Andrew Waterman
|
8087a205cc
|
Remove redundant check in interrupt priority encoding
chooseInterrupts already sorts M interrupts above S interrupts.
|
2017-08-17 22:23:42 -07:00 |
|
Andrew Waterman
|
cbe7c51b50
|
Respect ISA requirements on interrupt priority order
a62e76cb16
|
2017-08-17 21:27:08 -07:00 |
|
Henry Cook
|
4c595d175c
|
Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
|
2017-07-07 10:48:16 -07:00 |
|
Andrew Waterman
|
e1cc0a0a0e
|
Mask debug interrupts similarly to other interrupts (#847)
This makes single-step exceptions higher-priority than debug interrupts.
|
2017-07-06 12:03:24 -07:00 |
|
Megan Wachs
|
e1fe0f245b
|
debug: Don't reset debugint register, as none of the interrupt registers are.
|
2017-06-27 14:10:13 -07:00 |
|
Megan Wachs
|
136e4b6c27
|
debug: use consistent coding style (Reg(init ... ) vs RegInit)
|
2017-06-27 13:42:38 -07:00 |
|
Megan Wachs
|
3b9550ede3
|
debug: correctly declare reg_debugint
|
2017-06-27 13:42:38 -07:00 |
|
Megan Wachs
|
56839b2c62
|
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
|
2017-06-27 13:42:38 -07:00 |
|
Megan Wachs
|
665c2a349c
|
Correct Debug + WFI Interactions
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
|
2017-06-27 13:42:38 -07:00 |
|
Jacob Chang
|
e3e77d68e6
|
PTW now does not require atomic memory operations, so take out the requirement (#767)
Bug fix in CSR which manifest itself when compiling a config with no extension
|
2017-05-26 13:11:15 -07:00 |
|
Andrew Waterman
|
dbc5e7c494
|
Add TLB miss performance counters (#762)
|
2017-05-23 12:52:25 -07:00 |
|
Andrew Waterman
|
7eefc12705
|
Support vectored stvec interrupts, too
137812654e
|
2017-05-07 15:40:08 -07:00 |
|
Andrew Waterman
|
c6135a02df
|
Revert "rocket: hard-wire UXL/SXL fields to 0"
This reverts commit ea0714bfcb .
We've waffled on this matter in the priv spec: 326bec83de
|
2017-05-07 15:23:21 -07:00 |
|
Andrew Waterman
|
e23ee274f6
|
Size hartid field with NTiles, not XLen
|
2017-04-26 20:11:43 -07:00 |
|
Andrew Waterman
|
c36c171202
|
Use correct interrupt priority order
|
2017-04-24 02:01:15 -07:00 |
|
Andrew Waterman
|
a454edaaf7
|
Treat exceptions as steps for the purposes of single-stepping
|
2017-04-17 10:28:33 -07:00 |
|
Andrew Waterman
|
b9e042d2bf
|
Unconditionally write badaddr, possibly to zero
59d33f6b83
|
2017-04-12 13:35:02 -07:00 |
|
Andrew Waterman
|
470c6711a7
|
Do some CSE by hand, per @terpstra
|
2017-04-10 22:38:25 -07:00 |
|
Andrew Waterman
|
a43bf2feae
|
Add vectored interrupt support
4dcaa944ba
I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:
ba6d88466a
|
2017-04-08 00:29:45 -07:00 |
|
Megan Wachs
|
9de06f8c83
|
Merge remote-tracking branch 'origin/master' into debug_v013_pr
|
2017-03-30 08:01:11 -07:00 |
|
Andrew Waterman
|
fd39eadcd6
|
New PMP encoding
|
2017-03-30 00:36:23 -07:00 |
|
Andrew Waterman
|
3546c8d133
|
If any PMPs are supported, all CSRs exist
|
2017-03-30 00:36:23 -07:00 |
|
Megan Wachs
|
d8033b20fc
|
Merge remote-tracking branch 'origin/master' into debug_v013_pr
|
2017-03-29 14:58:04 -07:00 |
|
Andrew Waterman
|
4215f480ef
|
Write instruction to badaddr on illegal instruction traps
|
2017-03-28 00:56:14 -07:00 |
|
Megan Wachs
|
bb64c92906
|
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
|
2017-03-27 21:21:48 -07:00 |
|
Andrew Waterman
|
05cbdced78
|
Work around zero-entry vec issue in Chisel
|
2017-03-27 17:57:26 -07:00 |
|
Andrew Waterman
|
d42d8aaea7
|
Make SEIP writable
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
c7c357e716
|
Add local interrupts to core (but not yet to coreplex)
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
069858a20c
|
rocket: separate page faults from physical memory access exceptions
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
ea0714bfcb
|
rocket: hard-wire UXL/SXL fields to 0
a2a3346e73
|
2017-03-27 16:37:09 -07:00 |
|
Andrew Waterman
|
17b1ee3037
|
Default to 8 PMPs; support 0 PMPs
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
10c39cb8d6
|
Disable mprv in D-mode
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
59d6afa132
|
mideleg/medeleg not present without less-privileged traps
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
38808f55d5
|
Share PMP mask gen between I$ and D$
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
a4164348b4
|
Expose MXR to S-mode
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
0380aed329
|
PUM -> SUM
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
29414f3a23
|
Simplify interrupt-stack discipline
f2ed45b179
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
03fb334c4c
|
Take mprv calculation off critical path
|
2017-03-24 16:39:52 -07:00 |
|
Andrew Waterman
|
aace526857
|
WIP on PMP
|
2017-03-24 16:39:52 -07:00 |
|