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riscv/rocket-chip
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121 Commits 1 Branch 0 Tags
85e5ce046f848025cf2f20b18b042b46b56fd0af
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Author SHA1 Message Date
Henry Cook 85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Henry Cook 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
2013-08-15 16:39:30 -07:00
Henry Cook 784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook 9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Henry Cook 11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook 199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00
Henry Cook 4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
Henry Cook 2796de01bf new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:41:27 -07:00
Henry Cook 896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook 85fbb650c9 makefile support for new multithreading tests 2013-06-13 15:34:54 -07:00
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