This uses an reorder queue but doesn't check to ensure that the data it fetches
from the queue is actually in the queue before using it. It seems that during
correct operation this never breaks, but I'm trying to get the backup memory
port working again and this assertion fails with it enabled (without the
assertion the core just gets a bogus data beat dies).
Closes#16
This was recently changed to write out physical addresses for SCR file entries,
but to bring up the chip we need SCR offsets so we can write the uncore SCR
file over HTIF. This changes the map generator to generate both.
Without this change things happened to work anyway because the high bits were
getting dropped by the SCR file.
Right now there's no way to ensure that SCR addresses don't conflict within
RocketChip. Since upstream only has one of them this isn't a big deal, but we
want to add a whole bunch more to control all the IP on Hurricane.
This patch adds some Scala code to allocate registers inside the SCR file,
ensure they don't conflict, to provide names for SCRs, attach registers to the
SCR file, and generate a C header file that contains the addresses of every SCR
on a chip.
With this patch we'll be able to get rid of that constant in the testbench.
This also allows us to kill one of the Raven diffs, which is does pretty much
the same thing (just in a second SCR file, and hacked in).
Palmer DabbeltandPalmer Dabbelt
