Jacob Chang
ec3789b365
Add Cross Cover Property Library ( #1149 )
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Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend
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Frontend improvements
2017-11-09 17:44:38 -08:00
Wesley W. Terpstra
4ccdbecb63
Async covers ( #1085 )
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* cover: support covering cross-product of ready-valid
* tilelink: AsyncCrossing now has covers for all flow control logic
2017-11-01 11:03:45 -07:00
Andrew Waterman
a2b80100e2
Make PseudoLRU policy support non-power-of-2 sizes
2017-11-01 01:47:23 -07:00
Wesley W. Terpstra
2acff8d21f
util: delete old long-deprecated crossing code
2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7da2dc13669a
2017-10-05 00:26:44 -07:00
Henry Cook
d33737802a
util: add DontTouch trait with dontTouchPorts method
2017-10-02 19:36:34 -07:00
Wesley W. Terpstra
5323cf88dd
util: add Option.unzip
2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Henry Cook
e0b9f9213a
make halt_and_catch_fire Optional
2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721
tile: add halt_and_catch_fire signal
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for unrecoverable / fatal errors
2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615
rocket: base trait for reporting ecc errors
2017-09-21 14:58:47 -07:00
Andrew Waterman
dbf599f6a1
Support SynchronizerShiftReg(sync = 0)
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This makes it easier to parameterize code where the synchronizer
might not always be needed.
2017-09-20 00:05:07 -07:00
Andrew Waterman
9a175b0fb1
Statically report error correction/detection capability from ECC codes
2017-09-20 00:05:07 -07:00
Jacob Chang
b4fc5104d4
Add cover property API that can be refined through Config PropertyLibrary ( #998 )
2017-09-19 19:26:54 -07:00
Megan Wachs
641a8e7eab
test_mode_reset: Correct some gender issues. Tie off signals in the test harness
2017-09-15 16:36:35 -07:00
Megan Wachs
6cda4504ac
test_mode_reset: use a cleaner interface with bundles and options instead of individual signals
2017-09-15 12:30:39 -07:00
Megan Wachs
ffc514d1bc
test_mode_reset: Add missing file
2017-09-14 13:17:37 -07:00
Megan Wachs
82c00cb656
reset_catch: Allow Test Mode Overrides
2017-09-14 13:16:13 -07:00
Wesley W. Terpstra
5626cdd18f
util: add the IdentityModule, useful to dedup wires
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
2d93262f71
RationalCrossing: use ShiftQueues
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These are faster and small don't cost much more.
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd
ShiftQueue: added a helper object
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256
ShiftQueue: fix bug in !flow case
2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254
synchronizers: I learn how foldRight works
2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab
shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
2017-09-07 09:57:50 -07:00
Megan Wachs
3c4b472f66
shift regs: remove some unnecessary primitives, and add some that actually are necessary
2017-09-06 10:37:59 -07:00
Megan Wachs
777f052f95
regs: Add named/initial value ShiftRegister primitives so they are all in one place
2017-09-05 17:32:53 -07:00
Megan Wachs
e9e46db600
sync reg: Rename the file to reflect the more generic shift registers also in the file.
2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514
Synchronizers: remove some newlines and unncessary gen's
2017-09-05 15:17:21 -07:00
Megan Wachs
a3bc5f2e33
synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
2017-08-30 12:59:16 -07:00
Megan Wachs
8139014c9e
syncrhonizers: Remove unused sync from superclass
2017-08-30 12:33:03 -07:00
Megan Wachs
9dd6c4c32d
synchronizers: New chisel ways of cloning type and use simpler lambda function
2017-08-30 12:11:14 -07:00
Megan Wachs
bd32f0c122
synchronizers: properly pass parameters up to the superclass
2017-08-30 11:58:25 -07:00
Megan Wachs
483e63da19
synchronizers: Correctly pass the width through
2017-08-30 11:50:25 -07:00
Megan Wachs
451334ac73
Add 1-deep synchronizer register for output of AsyncQueue
2017-08-28 17:18:54 -07:00
Megan Wachs
85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
Megan Wachs
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
Megan Wachs
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
Megan Wachs
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
Megan Wachs
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
Megan Wachs
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
Megan Wachs
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
Megan Wachs
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
Wesley W. Terpstra
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
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This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
Andrew Waterman
bc298bf146
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Yunsup Lee
cb3529bbc3
util: tweak rational crossings to avoid mux in source
2017-07-31 15:10:15 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
