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Author SHA1 Message Date
Megan Wachs 777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00
Megan Wachs e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. 2017-09-05 15:54:25 -07:00
Megan Wachs 5df23c5514 Synchronizers: remove some newlines and unncessary gen's 2017-09-05 15:17:21 -07:00
Megan Wachs a3bc5f2e33 synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive 2017-08-30 12:59:16 -07:00
Megan Wachs 8139014c9e syncrhonizers: Remove unused sync from superclass 2017-08-30 12:33:03 -07:00
Megan Wachs 9dd6c4c32d synchronizers: New chisel ways of cloning type and use simpler lambda function 2017-08-30 12:11:14 -07:00
Megan Wachs bd32f0c122 synchronizers: properly pass parameters up to the superclass 2017-08-30 11:58:25 -07:00
Megan Wachs 483e63da19 synchronizers: Correctly pass the width through 2017-08-30 11:50:25 -07:00
Megan Wachs c473538e36 Merge remote-tracking branch 'origin/master' into async_reg 2017-08-28 17:19:03 -07:00
Megan Wachs 451334ac73 Add 1-deep synchronizer register for output of AsyncQueue 2017-08-28 17:18:54 -07:00
Megan Wachs 85c39b2f97 syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI 2017-08-24 17:47:04 -07:00
Megan Wachs 4e773f4738 syncregs: Use synchronizer primivites for LevelSyncCrossing 2017-08-24 17:42:31 -07:00
Megan Wachs 130b24355f syncregs: Use synchronizer primitives for IntXing 2017-08-24 17:39:07 -07:00
Megan Wachs 8b462d1595 syncregs: Use common primitives for AsyncQueue grey code synchronizers 2017-08-24 17:34:07 -07:00
Megan Wachs 3461cb47cc syncregs: Make Reset catcher use the synchronizer primitive 2017-08-24 17:26:38 -07:00
Megan Wachs c78ee9f0e4 syncreg: Refactor common code 2017-08-24 17:18:04 -07:00
Megan Wachs d83a6dc6af syncregs: Add utilities for Synchronizing Shift Registers 2017-08-24 16:55:17 -07:00
Megan WachsandGitHub bdaae40035 Merge pull request #973 from freechipsproject/named_buffers 
systemBus: allowing naming the TLBuffers which get inserted
 2017-08-24 16:31:14 -07:00
Megan Wachs 7f683eeb24 async_regs: Make modules have predictable names 2017-08-24 15:33:53 -07:00
Megan Wachs 0f75ebee92 async_reg: Rename the file to match scalastyle 2017-08-24 15:31:29 -07:00
Megan Wachs 103b6bc6d3 systemBus: allowing naming the TLBuffers which get inserted 2017-08-24 14:49:12 -07:00
Megan WachsandGitHub 6e689f55ed Merge pull request #965 from freechipsproject/quash_x 
async_reset_reg: Squash X's the same as for synchronous reg
 2017-08-21 16:48:25 -07:00
Megan Wachs 81890e3a42 async_reg: Clean up some funky indentation 2017-08-21 16:06:36 -07:00
Megan Wachs 4f45379863 async_reset_reg: Squash X's the same as for reset reg 2017-08-21 14:33:19 -07:00
Megan WachsandGitHub 1db4b3be9a Merge pull request #957 from freechipsproject/param_jtag_vpi 
jtag_vpi: Use Parameterized Black Box
 2017-08-14 18:37:30 -07:00
Megan Wachs 8783d51c97 jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed 2017-08-14 17:25:47 -07:00
Megan WachsandGitHub 57a5965bf4 Merge pull request #954 from freechipsproject/max-core-cycles 
Add a +max-core-cycles PlusArg
 2017-08-13 16:45:59 -07:00
Megan Wachs 88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Megan WachsandGitHub 017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar 
TLXbar: Allow more masters and slaves and issue a warning.
 2017-08-03 16:52:56 -07:00
Megan Wachs 50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Megan WachsandGitHub 3fc7100048 Merge pull request #917 from freechipsproject/fuzzer_order 
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
 2017-08-02 18:39:59 -07:00
Megan WachsandGitHub d9821a74ce Merge pull request #916 from freechipsproject/transfer_sizes_print 
diplomacy: Pretty Print for TransferSizes
 2017-08-02 16:56:36 -07:00
Megan Wachs 595415d207 TLFuzzer: Correct the number of ordered clients created 2017-08-02 15:48:21 -07:00
Megan Wachs fc5c04ed4b TLFuzzer: Allow Ordered clients to be created as well by the fuzzer 2017-08-02 14:44:18 -07:00
Megan Wachs 85bdae0fa8 diplomacy: Pretty Print for TransferSizes 2017-08-02 11:40:50 -07:00
Megan WachsandGitHub 07b4edfc87 Merge pull request #908 from freechipsproject/combo-breaker 
dcache: break potential combinatorial loop
 2017-07-31 16:13:01 -07:00
Megan WachsandGitHub 573890e102 Merge pull request #900 from freechipsproject/more_verbose_requires 
diplomacy: More verbose require
 2017-07-28 13:23:33 -07:00
Megan Wachs f61fe2be1e diplomacy: More verbose require 2017-07-28 10:05:45 -07:00
Megan WachsandWesley W. Terpstra f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) 2017-07-21 21:55:32 -07:00
Megan WachsandGitHub 35464782b5 PLIC: maxPriorities comes from params 2017-07-13 15:57:10 -07:00
Megan WachsandGitHub f646bed3ea PLIC: Use longer DTS name for Max Priorities. 
I used the singular because there is really only one max priority
 2017-07-13 13:37:22 -07:00
Megan WachsandGitHub 0800fd3ed9 PLIC: Add maxPri as well as ndev in DTS 2017-07-13 13:18:50 -07:00
Megan WachsandWesley W. Terpstra 177ccbb663 regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855) 2017-07-10 21:07:50 -07:00
Megan WachsandGitHub c28c23150d Merge pull request #850 from freechipsproject/plic_undefZero 
PLIC: (undefZero=true) Don't allow addresses to alias
 2017-07-06 18:39:10 -07:00
Megan WachsandGitHub 76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias 
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
 2017-07-06 17:57:08 -07:00
Megan WachsandGitHub 988caf5e34 Merge pull request #848 from freechipsproject/revert-839-bump-firrtl 
Revert "Bump firrtl"
 2017-07-05 22:32:45 -07:00
Megan WachsandGitHub 029886d0d5 Revert "Bump firrtl" 2017-07-05 21:13:47 -07:00
Megan WachsandGitHub 734a178e4e Merge pull request #846 from freechipsproject/travis-delete-caches 
Update README_TRAVIS.md
 2017-07-05 13:52:26 -07:00
Megan WachsandGitHub 94262ea950 Update README_TRAVIS.md 
add some headers
 2017-07-05 11:45:04 -07:00
Megan WachsandGitHub 84c2bf5504 Update README_TRAVIS.md 
Clarify when to delete caches
 2017-07-05 11:40:36 -07:00
Megan WachsandGitHub 85f37146d5 Merge pull request #842 from freechipsproject/fesvr-multi 
Bump FESVR for multi-core support
 2017-07-03 15:31:41 -07:00
Megan Wachs ddd2b2236d bump riscv-tools/riscv-fesvr to pick up multicore fixes 2017-07-03 13:25:05 -07:00
Megan Wachs 3d28c0182d travis: add a branch whitelist with just 'master'. 
Travis allows us to build on branch updates and on PRs. Right now our process is to build always on PRs, but to manually only build 'master' when we know that riscv-tools has been bumped (because that rebuilds the master cache which holds riscv-tools). But this is an annoying and error-prone processes that requires extra admin permissions.

With this change, i think we can just leave "Build Branch Updates" to "ON" and get the same effect we are currently doing manually, because only on update to master branch will it do a build. PRs to master branch will get a build. PRs to other branches will I believe NOT get a build.
 2017-07-03 13:25:05 -07:00
Megan WachsandGitHub 69ab3626ca Merge pull request #837 from freechipsproject/plic_recode 
plic: Recode to use OH knowledge
 2017-06-30 16:05:32 -07:00
Megan WachsandGitHub 8c92c50d85 plic: make assertion comment right 2017-06-30 14:25:09 -07:00
Megan Wachs f31ae008f3 plic: Clean up comments and simplify checking 2017-06-30 14:15:26 -07:00
Megan Wachs 76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs 3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Megan WachsandGitHub 237689b799 Merge pull request #838 from freechipsproject/more_plic 
plic: Use same recoding technique on complete as well as claim
 2017-06-30 11:06:27 -07:00
Megan Wachs e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Megan WachsandGitHub 834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Megan WachsandGitHub ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race 
debug: Fix race between resumereq and resumeack
 2017-06-29 13:38:20 -07:00
Megan Wachs 0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Megan WachsandGitHub 992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Megan Wachs 39b06a917f bump riscv-tools for fesvr-dont-die 2017-06-28 16:38:02 -07:00
Megan Wachs 35b89d8023 bump riscv-tools for fesvr-don't-die 2017-06-28 13:36:53 -07:00
Megan Wachs 3fc75c2714 debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. 2017-06-27 17:40:58 -07:00
Megan Wachs e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. 2017-06-27 14:10:13 -07:00
Megan Wachs 136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) 2017-06-27 13:42:38 -07:00
Megan Wachs 3b9550ede3 debug: correctly declare reg_debugint 2017-06-27 13:42:38 -07:00
Megan Wachs 56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) 2017-06-27 13:42:38 -07:00
Megan Wachs 665c2a349c Correct Debug + WFI Interactions 
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
 2017-06-27 13:42:38 -07:00
Megan WachsandGitHub d0f8cdd00c Merge pull request #804 from freechipsproject/travis_cache_stages 
travis: attempt to make 2 build stages for cache
 2017-06-16 07:31:56 -07:00
Megan WachsandGitHub 30a3e3ef55 travis: attempt to make 2 build stages for cache 
First stage builds riscv-tools, next stage builds verilator
 2017-06-15 21:31:15 -07:00
Megan WachsandGitHub d316aeb275 Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts 
Bump riscv-tools to pick up FESVR which allows starting all harts
 2017-06-15 13:55:46 -07:00
Megan Wachs 9a789fc0cf Bump riscv-tools to pick up FESVR which allows starting all harts 2017-06-15 11:05:07 -07:00
Megan WachsandGitHub f0a59a81c8 Merge pull request #783 from freechipsproject/plusarg_docstring 
plusarg_reader : Add the ability to add a documentation string.
 2017-06-05 18:21:07 -07:00
Megan Wachs 8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Megan WachsandGitHub 7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs 8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
Megan WachsandGitHub 8d04e0efb8 Merge pull request #771 from freechipsproject/jtag_vpi_tab 
JTAG VPI: Make it work without debug_pp flag
 2017-05-30 17:29:23 -07:00
Megan Wachs 6aa13b4e01 JTAG VPI: Make it work without debug_pp flag 2017-05-30 15:46:45 -07:00
Megan WachsandGitHub f61e30763f Merge pull request #768 from freechipsproject/flush_jtag_vpi 
jtag_vpi: Attempt to more aggressively flush the simulator output
 2017-05-26 15:51:43 -07:00
Megan Wachs 0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
Megan WachsandWesley W. Terpstra 24a533e77c debug: Bump riscv-tools to pick up correction in gdbserver 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 26194b3078 bump riscv-tools to pick up latest version of debug tests 2017-05-18 18:46:45 -07:00
Megan WachsandGitHub d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Megan WachsandGitHub f8c92d2669 Merge branch 'master' into pipeline-mmio 2017-05-03 08:37:12 -07:00
Megan Wachs 922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
Megan WachsandGitHub d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Megan Wachs 7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Megan WachsandAndrew Waterman e9db531e81 point to riscv-tools README for dependencies (#705) 
As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.
 2017-04-25 20:20:27 -07:00
Megan Wachs c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Megan Wachs 9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. 2017-04-20 10:19:50 -07:00
Megan Wachs cc7f0a5b7a debug: whitespace cleanup 2017-04-20 10:19:50 -07:00
Megan Wachs 5934779082 debug: Clean up ValidReg assertion. 2017-04-20 10:19:50 -07:00
Megan Wachs 0c013a56c0 debug: Make DMI NOPs really NOPs. 
This simplifies SW design and CDC issues.
 2017-04-20 10:19:50 -07:00
Megan Wachs 1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 2017-04-19 21:37:37 -07:00