 Andrew Waterman
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73d8d42515
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fix coherence bug with multiple probe replies
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2012-04-09 21:40:35 -07:00 |
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Andrew Waterman
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e38114e4b0
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fix coherence bug
popping wrong store dependence queue
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2012-03-16 01:24:07 -07:00 |
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Andrew Waterman
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77c405ffa1
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use broadcast hub and coherent HTIF
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2012-03-14 16:44:35 -07:00 |
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Andrew Waterman
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53cd543d3f
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fix minor coherence bugs
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2012-03-13 19:10:54 -07:00 |
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Andrew Waterman
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53d69d3006
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parameterize broadcast hub by # of tiles
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2012-03-13 17:12:01 -07:00 |
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Andrew Waterman
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1258f31825
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add probe unit
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2012-03-13 16:43:51 -07:00 |
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Andrew Waterman
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d777f1cb24
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fix null hub store ack bug
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2012-03-10 15:19:12 -08:00 |
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Andrew Waterman
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3a72ace057
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-09 02:08:55 -08:00 |
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Andrew Waterman
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df6ac34821
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coherence hub fixes
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2012-03-07 21:03:44 -08:00 |
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Andrew Waterman
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7929600874
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change D$ to use FourStateCoherence protocol
instead of ThreeStateIncoherence.
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2012-03-07 01:26:35 -08:00 |
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Andrew Waterman
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012b991ffe
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implement transaction finish messages
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2012-03-06 15:48:08 -08:00 |
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Andrew Waterman
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1024a460f2
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support memory transaction aborts
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2012-03-06 00:35:02 -08:00 |
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Andrew Waterman
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6ad7aa5cdc
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flip direction of ioPipe to match ioDecoupled
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2012-03-02 16:18:32 -08:00 |
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Andrew Waterman
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4c3f7a36ce
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clean up D$ store data unit
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2012-03-01 19:20:00 -08:00 |
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Andrew Waterman
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8b519e7ea8
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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eec369a1c7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
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Andrew Waterman
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7d331858e2
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
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Andrew Waterman
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71c8d3fd41
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reorganize directory structure
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2012-02-08 15:13:08 -08:00 |
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