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Author	SHA1	Message	Date
Wesley W. Terpstra	71f2445c62	Merge pull request #546 from ucb-bar/dev-zero ... Dev zero	2017-02-03 19:49:56 -08:00
Wesley W. Terpstra	d1744a5667	coreplex: zero memory channels is also allowed	2017-02-03 19:00:08 -08:00
Wesley W. Terpstra	a3e56cfa5e	rocketchip: add Zero device to the memory subsystem	2017-02-03 17:19:24 -08:00
Wesley W. Terpstra	b240505a15	rocketchip: move memory channel Xbar from coreplex to rocketchip ... We want to keep the banks split in the outer SoC if there is an L3. Furthermore, each channel might go to different memory subsystems, like DDR/HMC/Zero, from rocketchip.	2017-02-03 17:19:21 -08:00
Wesley W. Terpstra	fc9ea62d38	HeterogeneousBag: a handy container for differently parameterized bundles	2017-02-03 16:21:33 -08:00
Wesley W. Terpstra	7afe383db3	Ecc: detect uncorrectable errors also for SEC	2017-02-03 16:21:09 -08:00
Wesley W. Terpstra	7aba066e67	tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways	2017-02-03 16:20:27 -08:00
Wesley W. Terpstra	93b2fa197e	Artefact output (#545) ... * build: stop using empty .prm file * generator: general-purpose mechanism for creating elaboration artefacts	2017-02-02 19:24:55 -08:00
Jacob Chang	094b3bc2b1	Merge pull request #544 from ucb-bar/jchang ... Added access function	2017-02-02 14:56:23 -08:00
Jacob Chang	83a83c778a	Added range function in IdRange ... Added source accessor function in TLEdge	2017-02-02 12:35:57 -08:00
Andrew Waterman	8225676a86	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN ... See https://github.com/riscv/riscv-isa-sim/issues/76	2017-02-02 11:55:08 -08:00
Andrew Waterman	75edf42323	Set xPIE=1 on xRET ... We were setting xPIE=0 instead. This is a benign bug, but still a bug.	2017-02-02 11:55:08 -08:00
Wesley W. Terpstra	b2ee5e7d38	Merge pull request #540 from ucb-bar/dedup ... Dedup rocket	2017-01-31 17:16:43 -08:00
Wesley W. Terpstra	9ca8f514c0	rocket: creating Bundles in an object also break dedup!	2017-01-31 14:45:11 -08:00
Wesley W. Terpstra	e1577bb06e	chisel3: bump chisel3 for work deduplication	2017-01-31 14:20:07 -08:00
Wesley W. Terpstra	e5af59db68	rocketchip: work-around ucb-bar/chisel3#472	2017-01-31 14:20:02 -08:00
Wesley W. Terpstra	9c0cc6fdf4	Merge pull request #537 from ucb-bar/l2-banks-together ... BankedL2Config: use the same LazyModule for all L2 banks	2017-01-30 15:39:04 -08:00
Wesley W. Terpstra	dc66c8857f	diplomacy: be more robust using Java introspection ... If an error occures, some objects might only be partially initialized. We want to still be able to get nice names for error messages.	2017-01-30 14:25:12 -08:00
Wesley W. Terpstra	280af9684b	BankedL2Config: use the same LazyModule for all L2 banks ... This makes it much easier for banked coherence managers to support cross-bank functionality, like a common control port, for example.	2017-01-30 14:02:59 -08:00
Henry Cook	b567a2a356	Merge pull request #536 from ucb-bar/diplomacy-star-nodes ... diplomacy: add :*= and :=* to support flexible # of edges	2017-01-30 11:19:33 -08:00
Wesley W. Terpstra	f7f52cc722	diplomacy: restore Monitor functionality	2017-01-29 17:25:14 -08:00
Wesley W. Terpstra	972953868c	uncore: switch to new diplomacy Node API ... Most adapters should work on multiple ports. This patch changes them all.	2017-01-29 15:54:45 -08:00
Wesley W. Terpstra	4d646939b0	diplomacy: make flexible-port adapters possible	2017-01-29 14:26:02 -08:00
Wesley W. Terpstra	24ee7f45f5	rocketchip: pass variable l1tol2 connections into coreplex	2017-01-29 11:18:36 -08:00
Wesley W. Terpstra	d5fa159063	diplomacy: add :*= and :=* to support flexible # of edges	2017-01-28 21:32:36 -08:00
Wesley W. Terpstra	03f2fe02ac	coreplex: support rational crossing to L2 (#534)	2017-01-27 17:09:43 -08:00
Richard Xia	61fbe62112	Ignore the built firrtl.jar. (#532)	2017-01-27 13:04:15 -08:00
Wesley W. Terpstra	19c58630d2	Merge pull request #533 from ucb-bar/rational-crossing ... Rational clock crossing	2017-01-26 22:30:04 -08:00
Wesley W. Terpstra	830d01329d	RationalCrossing: add some documentation	2017-01-26 21:27:34 -08:00
Wesley W. Terpstra	fc3b72084f	tilelink2: add a rational clock crossing adapter	2017-01-26 20:07:28 -08:00
Wesley W. Terpstra	4b70386393	AsyncCrossing: disambiguate the file name	2017-01-26 20:07:28 -08:00
Wesley W. Terpstra	5cf4b0632d	RationalCrossing: clock crossing between related clock domains	2017-01-26 20:07:28 -08:00
Jack Koenig	1285fa909f	Bump chisel and firrtl (#531)	2017-01-26 17:29:26 -08:00
Jim Lawson	3c1dac8c68	Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. (#526) ... This anticipates ucb-bar/chisel3#448. When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.	2017-01-26 11:11:14 -08:00
Henry Cook	0fe2899c74	[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)	2017-01-25 12:10:49 -08:00
Wesley W. Terpstra	d1dedd25e7	Merge pull request #529 from ucb-bar/physical-optimization ... Physical optimization	2017-01-24 18:59:07 -08:00
Wesley W. Terpstra	6ff35a387a	tilelink2: disable A=>D bypass in ToAXI4 whenever possible	2017-01-24 18:11:00 -08:00
Wesley W. Terpstra	64e1de751d	axi4: add a minLatency parameter	2017-01-24 18:11:00 -08:00
Wesley W. Terpstra	46cdfc2b45	diplomacy: find names of LazyModules also in Seq() member values (#527)	2017-01-24 18:10:37 -08:00
Wesley W. Terpstra	3fc55298ef	coreplex: provide coherence managers with geometry information	2017-01-23 15:50:39 -08:00
Wesley W. Terpstra	d4b3a0f0be	diplomacy: support given bits in AddressDecoder	2017-01-23 15:50:39 -08:00
Wesley W. Terpstra	c0b6d31377	tilelink2: Delayer adapter useful for unit tests	2017-01-23 15:50:39 -08:00
Wesley W. Terpstra	b3ef146805	Merge pull request #523 from ucb-bar/buffer-move ... coreplex: move TLBuffers for L2 and socBus	2017-01-21 14:53:51 -08:00
Wesley W. Terpstra	38c9ddffcc	BankedL2: move TLFilter BEFORE coherence manager ... This lets smart caches exclude the sets that are filtered.	2017-01-21 13:23:07 -08:00
Wesley W. Terpstra	dcadd5a006	coreplex: move TLBuffers for L2 and socBus	2017-01-20 22:23:36 -08:00
Wesley W. Terpstra	e8ce32a156	Merge pull request #515 from ucb-bar/cache-cork ... Cache cork	2017-01-19 20:00:51 -08:00
Wesley W. Terpstra	9dc7f180b6	diplomacy: support zero-port Nodes	2017-01-19 19:08:01 -08:00
Wesley W. Terpstra	c0496fab29	regression: disable build that times out on Travis	2017-01-19 19:07:59 -08:00
Wesley W. Terpstra	5d70265e86	rocket: L1 only needs cache-line transfer sizes	2017-01-19 19:07:14 -08:00
Wesley W. Terpstra	3a5e5a65f8	coreplex: support multiple memory channels via diplomatic trickery	2017-01-19 19:07:14 -08:00