riscv/rocket-chip
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1737 Commits

Author SHA1 Message Date
Wesley W. Terpstra
f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) 
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
 2017-07-26 10:21:31 -07:00
Andrew Waterman
5a5b78b15e Improve L2 TLB coding style 2017-07-26 02:22:43 -07:00
Andrew Waterman
5a9c673f41 Fix L2 TLB response bug 
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
 2017-07-26 02:20:41 -07:00
Andrew Waterman
acca0fccf5 Fix BTB not being refilled on some indirect jumps 
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
 2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) 2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend 
Acquire before release; jump in frontend
 2017-07-25 16:26:47 -07:00
Wesley W. Terpstra
c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888) 
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.

However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.

To solve this, we alternate an a.source bit every time D completes a txn.
 2017-07-25 16:23:55 -07:00
Andrew Waterman
15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Andrew Waterman
62c4080585 Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Andrew Waterman
66d06460fa Add option for acquire-before-release 2017-07-25 15:19:16 -07:00
Andrew Waterman
86ccd935fc Add method to print perf events 2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea Add L2 TLB miss counter 2017-07-25 15:19:16 -07:00
Andrew Waterman
3ced04b70a Mix in trait to connect global_reset_vector 2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668 coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887) 2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a fix HasRTCModuleImp (#885) 2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) 2017-07-21 21:55:32 -07:00
Yunsup Lee
21954c1c73 tileink: FIFOFixer should cope with zero-latency devices 2017-07-19 19:38:27 -07:00
Howard Mao
4d784ad693 add cloneType to RegisterWriteIO and RegisterReadIO (#874) 2017-07-18 18:52:31 -07:00
Wesley W. Terpstra
a9c58e9d9f diplomacy: support creating ShiftQueues as well 2017-07-18 14:57:02 -07:00
Wesley W. Terpstra
c0a3bb58e9 ShiftQueue: use Vec of Bool to support constant prop of enq.valid 2017-07-18 14:56:59 -07:00
Wesley W. Terpstra
416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) 2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
d09a985729 zero: fix attachment in multichannel case (#870) 2017-07-17 21:48:31 -07:00
Wesley W. Terpstra
fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) 2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784 fix the TLFuzzer IO (#869) 2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) 2017-07-14 16:13:30 -07:00
Richard Xia
9ade7af013 Merge pull request #862 from freechipsproject/plic-max-pri-dts 
PLIC: Add maxPri as well as ndev in DTS
 2017-07-13 17:08:21 -07:00
Richard Xia
f0481801df Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts 
Rename offchip-interrupts to external-interrupts.
 2017-07-13 16:52:57 -07:00
Megan Wachs
35464782b5 PLIC: maxPriorities comes from params 2017-07-13 15:57:10 -07:00
Richard Xia
d62787357b Rename offchip-interrupts to external-interrupts. 2017-07-13 15:56:22 -07:00
Shreesha Srinath
f2533ce825 bootrom: Adding bootrom parameters (#857) 
BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
 2017-07-13 13:40:02 -07:00
Megan Wachs
f646bed3ea PLIC: Use longer DTS name for Max Priorities. 
I used the singular because there is really only one max priority
 2017-07-13 13:37:22 -07:00
Megan Wachs
0800fd3ed9 PLIC: Add maxPri as well as ndev in DTS 2017-07-13 13:18:50 -07:00
Wesley W. Terpstra
b7f1ba3428 tilelink: FIFOFixer must support null cases (#860) 
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
 2017-07-12 22:20:31 -07:00
Wesley W. Terpstra
4eface8a9e rocket: do not require FIFO order for memory-like regions 2017-07-12 17:39:00 -07:00
Wesley W. Terpstra
09b9d33a9a tilelink: FIFOFixer now has a policy parameter 2017-07-12 17:38:55 -07:00
Wesley W. Terpstra
b363a94480 diplomacy: add a new UNCACHEABLE RegionType 2017-07-12 16:31:50 -07:00
Wesley W. Terpstra
c8a7648169 diplomacy: only evaluate a Nexus node's map function once 2017-07-12 16:20:55 -07:00
Wesley W. Terpstra
af3976aa67 regmapper: add byte-sized RegField helper function (#854) 2017-07-10 21:08:02 -07:00
Megan Wachs
177ccbb663 regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855) 2017-07-10 21:07:50 -07:00
Jim Lawson
287219da06 Merge pull request #851 from freechipsproject/chisel3clock 
Use chisel3 Clock() method.
 2017-07-10 08:33:46 -07:00
Wesley W. Terpstra
5db0e770d5 tilelink: TestSRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
702143eb33 tilelink: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
9310a33e77 apb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
28fbf1af8e ahb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
df44b23956 axi4: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
b2cc4b99ed tilelink: TestSRAM reports errors on illegal access 2017-07-07 21:40:36 -07:00
Wesley W. Terpstra
e8cb6dafd3 tilelink: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
f1fb3be603 ahb: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
19851a7c9e apb: SRAM reports errors on illegal access 2017-07-07 21:15:33 -07:00
Wesley W. Terpstra
025f7d890b axi4: SRAM now reports errors on illegal address (#852) 2017-07-07 19:27:32 -07:00
Jim Lawson
2bf91a0558 Use chisel3 Clock() method. 2017-07-07 14:16:39 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Megan Wachs
76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias 
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
 2017-07-06 17:57:08 -07:00
Andrew Waterman
a0cbc376b4 Merge pull request #849 from freechipsproject/l2-tlb 
L1 memory system improvements
 2017-07-06 13:03:06 -07:00
Andrew Waterman
e1cc0a0a0e Mask debug interrupts similarly to other interrupts (#847) 
This makes single-step exceptions higher-priority than debug interrupts.
 2017-07-06 12:03:24 -07:00
Andrew Waterman
b2351c5fbf Use consistent casing 2017-07-06 11:16:56 -07:00
Andrew Waterman
be4eceec0d Fix stupid D$ probe bug 2017-07-06 01:20:47 -07:00
Andrew Waterman
90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Andrew Waterman
438abc76d2 Handle TL errors in L1 I$ 
Cache the error bit in the tag array; report precisely on access.
 2017-07-06 01:02:11 -07:00
Andrew Waterman
0ef45fac9b Add tag ECC to D$ 2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae Improve probe state machine 
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
 2017-07-03 16:25:04 -07:00
Richard Xia
5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. 2017-06-30 17:44:16 -07:00
Megan Wachs
69ab3626ca Merge pull request #837 from freechipsproject/plic_recode 
plic: Recode to use OH knowledge
 2017-06-30 16:05:32 -07:00
Megan Wachs
8c92c50d85 plic: make assertion comment right 2017-06-30 14:25:09 -07:00
Megan Wachs
f31ae008f3 plic: Clean up comments and simplify checking 2017-06-30 14:15:26 -07:00
Megan Wachs
76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Wesley W. Terpstra
367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Megan Wachs
0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Henry Cook
6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
66489ffa13 rom+sram: add a compatible field 2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958 TLZero: include a version number 2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
5436be54ff periphery: use SimpleBus for mmio ports 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
171e1a4c05 diplomacy: add SimpleBus to describe bridges 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
0bf46edb6c diplomacy: support reg-names in DTS output 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
6c2b770605 plic: do not output #address-cells 
This is only needed for an interrupt-map, not an interrupt-controller.
 2017-06-28 14:26:55 -07:00
Andrew Waterman
b9a934ae28 Support eccBytes > 1 2017-06-28 02:09:18 -07:00
Andrew Waterman
8e4be40efc Propagate wb_reg_rs2 for sfence ASID 
This would have been a bug if we supported ASIDs.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
2077e4190b Make log more sensible for long-latency operations 
Show only one write to the destination register, not two.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
6f8fdff762 Basic L1 D$ ECC support 
Only supports ECC on data, not tags; only supports byte granularity.
 2017-06-28 02:09:18 -07:00