Logo
Explore Help
Sign In
riscv/rocket-chip
Watch 1
Star 0
Fork 0
Code Releases Activity
53 Commits 1 Branch 0 Tags
6d3bba6cffcad38c76bce1c7e6d02f501caefc41
Commit Graph
5 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Matthew NaylorandHenry Cook 6d3bba6cff Tweaks to README.md
Remove occurrences of ../scripts/ and instead state that it must be in
your PATH.  Also drop the content introducing the isit script as
tracegen+check.sh subsumes this.
2016-03-31 14:22:09 -07:00
Matthew Naylor bda5772e98 Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too. 2016-03-18 12:11:11 +00:00
Matthew NaylorandHoward Mao 04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. 2016-03-16 12:54:19 -07:00
Matthew Naylor 1b6871f3d8 Add author, affiliation, and sponsor info to trace-generator files. 2016-02-23 15:30:11 +00:00
Matthew NaylorandHoward Mao e63fc3bb44 Added trace generator 2016-02-22 08:43:34 -08:00
Powered by Gitea Version: 1.27.1 Page: 12ms Template: 3ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API