Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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Andrew Waterman
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9af86633d7
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invalidate I$ prefetcher when invalidating I$
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2012-02-17 17:56:01 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Andrew Waterman
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a1855b12c2
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clean up queues
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2012-02-08 17:55:05 -08:00 |
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Christopher Celio
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1be9d15944
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache
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2012-02-07 14:07:42 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Rimas Avizienis
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b2894671f6
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2011-11-30 21:55:13 -08:00 |
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Rimas Avizienis
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bc44572d99
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bugfixes due to new hcl jar file
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2011-11-30 21:54:55 -08:00 |
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Andrew Waterman
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8f3927fdfa
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queue data type is now templated
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2011-11-30 18:08:26 -08:00 |
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Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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