riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra
0fe625c52f diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
dfb6340927 Merge pull request #755 from freechipsproject/verilator-plusargs 
Verilator plusargs
 2017-06-01 14:34:09 -07:00
Wesley W. Terpstra
6a7e6ab325 plusarg_reader: support verilator 2017-06-01 10:59:45 -07:00
Wesley W. Terpstra
9eae1fa377 verilator: bump to version 3.904 2017-06-01 10:59:39 -07:00
Yunsup Lee
6124bf0cc2 sort entires in the printed address map (#773) 2017-05-31 07:45:46 -10:00
Jack Koenig
8e45dd9352 Bump firrtl to get performance bug fixes (#772) 2017-05-30 20:21:29 -07:00
Megan Wachs
8d04e0efb8 Merge pull request #771 from freechipsproject/jtag_vpi_tab 
JTAG VPI: Make it work without debug_pp flag
 2017-05-30 17:29:23 -07:00
Megan Wachs
6aa13b4e01 JTAG VPI: Make it work without debug_pp flag 2017-05-30 15:46:45 -07:00
Megan Wachs
f61e30763f Merge pull request #768 from freechipsproject/flush_jtag_vpi 
jtag_vpi: Attempt to more aggressively flush the simulator output
 2017-05-26 15:51:43 -07:00
Jacob Chang
e3e77d68e6 PTW now does not require atomic memory operations, so take out the requirement (#767) 
Bug fix in CSR which manifest itself when compiling a config with no extension
 2017-05-26 13:11:15 -07:00
Megan Wachs
0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
Andrew Waterman
618468a06b Make plusarg_reader default args work with VCS (#765) 
Resolves #764
 2017-05-24 21:38:56 -07:00
Andrew Waterman
dbc5e7c494 Add TLB miss performance counters (#762) 2017-05-23 12:52:25 -07:00
Andrew Waterman
b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Henry Cook
940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Wesley W. Terpstra
7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) 
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
 2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
20704b1454 Merge pull request #753 from freechipsproject/debug_tests 
Debug Tests
 2017-05-18 22:20:21 -07:00
Megan Wachs
24a533e77c debug: Bump riscv-tools to pick up correction in gdbserver 2017-05-18 18:46:46 -07:00
Megan Wachs
304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools 2017-05-18 18:46:46 -07:00
Megan Wachs
26194b3078 bump riscv-tools to pick up latest version of debug tests 2017-05-18 18:46:45 -07:00
Colin Schmidt
ada5439c3e dont use env to force caches to be the same (#754) 2017-05-18 18:46:29 -07:00
Wesley W. Terpstra
55e8d28868 Merge pull request #747 from freechipsproject/try-travis-stages 
try using a new travis staging feature
 2017-05-18 14:14:54 -07:00
Colin Schmidt
d0c00eccb9 caches don't transfer across sudo flag changes 2017-05-18 11:33:23 -07:00
Colin Schmidt
617dd6fe1e try travis suggestion on the jvm stages 2017-05-18 11:06:43 -07:00
Jack Koenig
08eb7b0410 Bump firrtl for bug fixes in annotation propagation and DCE (#751) 2017-05-18 10:54:30 -07:00
Henry Cook
991a67ac68 Merge pull request #749 from freechipsproject/unit-test-speedup 
Unit test speedup
 2017-05-17 16:28:42 -07:00
Henry Cook
733ebbce0e Update README.md (#748) 2017-05-17 14:53:56 -07:00
Colin Schmidt
66d660ff60 use YAML to condense script replication 2017-05-17 14:41:04 -07:00
Wesley W. Terpstra
748a48f667 unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
bea2489507 unittest: make overall test duration configurable 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
c8ba6b2feb unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442 unit tests: all should accept timeout override 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
4acc302158 unittest: disable XBar test from regression (covered by other tests) 2017-05-17 14:02:59 -07:00
Colin Schmidt
0c382204d4 give them all stages 2017-05-17 12:38:52 -07:00
Colin Schmidt
62a54e6bdb inline the env matrix 2017-05-17 12:36:49 -07:00
Colin Schmidt
2f3e22aff6 matrix outside after jobs 2017-05-17 12:34:11 -07:00
Colin Schmidt
f3775cbbbf try moving matrix into jobs 2017-05-17 12:31:13 -07:00
Henry Cook
dfabf68d9c Merge pull request #746 from freechipsproject/fix-bundle-refs 
diplomacy: provide connect access to edges without bundles
 2017-05-17 12:28:46 -07:00
Colin Schmidt
b7dc415522 maybe this will order them with deploy last 2017-05-17 12:28:01 -07:00
Colin Schmidt
b9fc169367 try another stages organization 2017-05-17 12:24:41 -07:00
Colin Schmidt
83a5230e91 change install to script? 2017-05-17 12:13:31 -07:00
Colin Schmidt
bce613ce38 try using a new travis staging feature 
The idea is to let us avoid building the tools
for each SUITE
 2017-05-17 11:58:09 -07:00
Wesley W. Terpstra
8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer 2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument 2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800 diplomacy: provide connect access to edges without bundles 
Forcing the bundles to exist early can mess up module ownership.
 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
65053978dc Merge pull request #745 from freechipsproject/tile-xbar 
Tile xbar
 2017-05-17 06:28:37 -07:00
Megan Wachs
d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00
Henry Cook
a19fc2549e tile: add tileBus xbar 2017-05-16 16:12:01 -07:00