This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
We were zero-extending it, which is a double-precision zero in the recoded
format. So, when spilled and reloaded with fsd/fld, the original value
was destroyed. Instead, set the MSBs so that it represents sNaN. When
spilled, the single-precision number will be preserved as the NaN payload.
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
In order to ensure that verilator is happy, we launch both clocks from a
clock divider. Sadly, it does not follow the spec wrt. derived clocks.
See the verilator manual section on "Generated Clocks".
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.
See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.
This patch adds targets:
run-regression-tests-fst
run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
