Wesley W. Terpstra
5626cdd18f
util: add the IdentityModule, useful to dedup wires
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
2d93262f71
RationalCrossing: use ShiftQueues
...
These are faster and small don't cost much more.
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd
ShiftQueue: added a helper object
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256
ShiftQueue: fix bug in !flow case
2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254
synchronizers: I learn how foldRight works
2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab
shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
2017-09-07 09:57:50 -07:00
Megan Wachs
3c4b472f66
shift regs: remove some unnecessary primitives, and add some that actually are necessary
2017-09-06 10:37:59 -07:00
Megan Wachs
777f052f95
regs: Add named/initial value ShiftRegister primitives so they are all in one place
2017-09-05 17:32:53 -07:00
Megan Wachs
e9e46db600
sync reg: Rename the file to reflect the more generic shift registers also in the file.
2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514
Synchronizers: remove some newlines and unncessary gen's
2017-09-05 15:17:21 -07:00
Megan Wachs
a3bc5f2e33
synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
2017-08-30 12:59:16 -07:00
Megan Wachs
8139014c9e
syncrhonizers: Remove unused sync from superclass
2017-08-30 12:33:03 -07:00
Megan Wachs
9dd6c4c32d
synchronizers: New chisel ways of cloning type and use simpler lambda function
2017-08-30 12:11:14 -07:00
Megan Wachs
bd32f0c122
synchronizers: properly pass parameters up to the superclass
2017-08-30 11:58:25 -07:00
Megan Wachs
483e63da19
synchronizers: Correctly pass the width through
2017-08-30 11:50:25 -07:00
Megan Wachs
451334ac73
Add 1-deep synchronizer register for output of AsyncQueue
2017-08-28 17:18:54 -07:00
Megan Wachs
85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
Megan Wachs
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
Megan Wachs
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
Megan Wachs
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
Megan Wachs
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
Megan Wachs
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
Megan Wachs
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
Megan Wachs
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
Wesley W. Terpstra
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
...
This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
Andrew Waterman
bc298bf146
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Yunsup Lee
cb3529bbc3
util: tweak rational crossings to avoid mux in source
2017-07-31 15:10:15 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Wesley W. Terpstra
c0a3bb58e9
ShiftQueue: use Vec of Bool to support constant prop of enq.valid
2017-07-18 14:56:59 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Andrew Waterman
9c78ac4d78
Add grouped method to AugmentedUInt, like Seq.grouped
2017-06-28 02:09:18 -07:00
Wesley W. Terpstra
2d8b2f4edd
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
Wesley W. Terpstra
11d1cb02eb
util ReduceOthers produces nlogn cost ready-valid logic
2017-06-22 19:43:20 -07:00
Shreesha Srinath
4059d9417f
GeneratorUtils: support to elaborate a RawModule
2017-06-15 14:33:02 -07:00
Megan Wachs
7afd5e6070
remove unnecessary whitespace. Fix grammar.
2017-06-05 16:18:57 -07:00
Megan Wachs
8440c4b1c4
plusarg_reader : Add the ability to add a documentation string.
2017-06-05 16:16:52 -07:00
Andrew Waterman
0ffb2c8baf
Simplify and improve QoR of ShiftQueue
2017-06-02 20:44:52 -07:00
Wesley W. Terpstra
7f1d3c445f
Plusargs -- tilelink timeout detection from the command line ( #752 )
...
* util: PlusArg gives Chisel access to the command-line
* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
3e2b477c0a
rational: adjust comments and add a case for N:M
2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
2119df5a60
vsrc: add ClockDivider3 used to simulate unaligned clocks
2017-05-14 15:05:55 -07:00
Andrew Waterman
ee6702e5e0
Support indexing 1-entry Seqs
...
It's a zero-width wire special case.
Closes #706 .
2017-04-26 19:35:35 -07:00
Henry Cook
9bb0d92381
Merge branch 'master' into async_queue_option
2017-04-25 11:23:22 -07:00
Andrew Waterman
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9
Add ShiftQueue; use it
2017-04-24 02:01:15 -07:00
Ben Keller
0aa8f7d61d
Add narrowData option to AsyncQueue.
...
This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
2017-04-21 16:31:17 -07:00
Wesley W. Terpstra
b4d17c76d1
coreplex: make rational+synchronous crossing configurable ( #688 )
2017-04-19 16:16:05 -07:00
Wesley W. Terpstra
6aeec673f2
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
Andrew Waterman
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
Megan Wachs
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00