  Colin SchmidtandGitHub
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aced18b3bb
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Move RoCC interface to Diplomacy and TL2 (#807)
* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
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2017-06-22 12:07:09 -07:00 |
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Colin SchmidtandGitHub
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675f183dd2
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refactor ICache to be reusable by other frontends (#808)
* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
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2017-06-20 08:21:01 -07:00 |
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 Colin SchmidtandWesley W. Terpstra
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ada5439c3e
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dont use env to force caches to be the same (#754)
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2017-05-18 18:46:29 -07:00 |
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Colin SchmidtandWesley W. Terpstra
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f19d504c88
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Use % in makefrag-verilog to prevent double firrtl execution (#452)
* Use % in makefrag-verilog to prevent double firrtl execution
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2016-11-25 01:50:01 -08:00 |
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 Colin SchmidtandAndrew Waterman
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737cf82478
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Print out seed if we can (#412)
Now that we have ifdef VCS in here lets use it for something more than compatibility
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2016-10-24 12:36:29 -07:00 |
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Colin Schmidt
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cb8878c931
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Don't build any hurricane branches
Don't mean to eat up travis bandwidth but shared branches sometimes get made.
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2016-10-21 16:26:41 -07:00 |
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Colin SchmidtandGitHub
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2522bdd7b8
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Merge pull request #321 from ucb-bar/add-multiclock-coreplex
add multiclock support to Coreplex
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2016-09-21 17:23:34 -07:00 |
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Colin SchmidtandAndrew Waterman
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a10d058e1a
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fix warnings in verilog source (#274)
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2016-09-12 18:25:35 -07:00 |
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Colin SchmidtandAndrew Waterman
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92718e4b61
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fix null statement in vsli_mem_gen ala firrtl#264 (#252)
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2016-09-07 11:04:36 -07:00 |
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Colin SchmidtandAndrew Waterman
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a43ad522dc
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add clock override to tile constructor (#42)
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
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2016-07-21 17:56:52 -07:00 |
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Colin SchmidtandGitHub
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ba35712f08
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Merge pull request #140 from ucb-bar/verilator
Default to Chisel 3
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2016-06-15 16:25:07 -07:00 |
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Colin SchmidtandAndrew Waterman
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e3816d5fc7
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set invalidate_lr in other rocc examples (#47)
This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
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2016-06-14 16:59:37 -07:00 |
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Colin SchmidtandAndrew Waterman
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2c325151bf
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pass invalidate_lr through simple cache interface (#45)
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2016-06-09 17:22:36 -07:00 |
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Colin SchmidtandAndrew Waterman
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8516e38eb2
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remove implicit modulo addressing in FPU (#44)
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2016-06-09 11:33:33 -07:00 |
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Colin Schmidt
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c080e82e92
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Merge pull request #34 from seldridge/rocketchip-addons-build
build.scala uses space-delimited ROCKETCHIP_ADDONS
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2015-12-09 11:57:19 -08:00 |
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Colin Schmidt
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7259239ba4
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Merge pull request #31 from ucb-bar/multirocc
implement support for multiple RoCC accelerators
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2015-11-28 08:56:07 -05:00 |
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Colin Schmidt
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90991014a0
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Merge pull request #19 from ucb-bar/multirocc
Add support for multiple RoCC accelerators
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2015-11-28 08:56:04 -05:00 |
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Colin Schmidt
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97d0e195ae
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Merge pull request #28 from ucb-bar/yusnup
Don't re-generate the .d files on "make clean"
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2015-11-12 00:46:21 -08:00 |
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Colin Schmidt
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032bdd0601
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Merge pull request #24 from ucb-bar/regression-master
Add a "--master" flag to the regression script
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2015-10-29 14:15:44 -07:00 |
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