Wesley W. Terpstra
53f030c037
TLSplitter: default policy is roundRobin
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Track commit 274d908d98
2017-06-20 14:03:01 -07:00
Wesley W. Terpstra
1aa4f5ce33
TLSplitter: QoR improvements
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Track commit 985d9750e6
2017-06-20 14:01:07 -07:00
Wesley W. Terpstra
f6e0dd12c8
TLSplitter: ManagerUnification is not used in Xbars
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Track the change made in 5994714970
2017-06-20 13:58:30 -07:00
Henry Cook
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
Wesley W. Terpstra
4a15d47061
diplomacy: BufferParams can now directly create a Queue
2017-06-14 13:47:37 -07:00
Wesley W. Terpstra
94f85e8bc8
tilelink2: TLMonitor will not create giant wires
2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e
add a debug print for xbar id mappings
2017-06-13 16:58:21 -07:00
Henry Cook
2e8a40a23f
diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules
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And add a MonitorBase class to be connect's return type.
2017-06-13 13:55:27 -07:00
Leway Colin
60c896b48c
Typo: is should be if ? ( #786 )
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Typo: is should be if ?
2017-06-07 10:40:13 -07:00
Wesley W. Terpstra
87a5665e43
axi4: only block writes if SAME master has outstanding reads ( #782 )
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* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
2017-06-05 16:54:00 -07:00
solomatnikov
274d908d98
Changed TLXbar arbitration policy to roundRobin ( #781 )
2017-06-05 10:20:28 -07:00
Wesley W. Terpstra
d002cec6ac
NodeNumberer: add an adapter to map inter-chip fabrics
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
5a2a6b0386
diplomacy: add a CustomNode type that allows direct overload of methods
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
fed1f53afa
tilelink2: add a TLSplitter to be used for the ISP port
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
a4bf678954
tilelink2: fix latent Xbar truncation bug
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This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
ce12a64f4b
tilelink2: support SplitterNodes
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
de39af7f65
tilelink2: make some Xbar methods reusable
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
e0741a2097
axi4: don't map unused masters into TL source ID space
2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
ae8734da05
diplomacy: report cacheability in ResourceAddress
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6
tilelink2: Xbar QoR improvement
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
9317a00896
tilelink2: ToAXI4, sort and print AXI IDs used
2017-06-02 14:27:37 -07:00
Wesley W. Terpstra
eb14329c63
tilelink2: only combine managers of the same resources
2017-06-01 15:34:43 -07:00
Wesley W. Terpstra
1f531b1593
tilelink2: improve round robin arbiter QoR
2017-06-01 15:34:40 -07:00
Wesley W. Terpstra
5994714970
diplomacy: move manager unification to meta-data only
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Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
0fe625c52f
diplomacy: improve PMA circuit QoR
2017-06-01 15:30:20 -07:00
Henry Cook
940614625e
TLCacheCork: unsafe flag now _really_ unsafe ( #760 )
2017-05-22 19:37:11 -07:00
Wesley W. Terpstra
7f1d3c445f
Plusargs -- tilelink timeout detection from the command line ( #752 )
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* util: PlusArg gives Chisel access to the command-line
* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
c8ba6b2feb
unittests: accept a configurable number of transactions to run
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442
unit tests: all should accept timeout override
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
8c3736e0dc
tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer
2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3
diplomacy: appease Jack by removing unused 1st bundles argument
2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2
tilelink2: don't widen TLMonitor interface unnecessarily
2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800
diplomacy: provide connect access to edges without bundles
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Forcing the bundles to exist early can mess up module ownership.
2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
3e2b477c0a
rational: adjust comments and add a case for N:M
2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
05e7501e7a
build: include chiselName and give an example of using it ( #738 )
2017-05-12 06:25:58 -07:00
Henry Cook
5f3a4ada1b
diplomacy: add legalize method to AddressSet
2017-05-10 12:54:24 -07:00
Henry Cook
3af40bff8b
tilelink: better address masking for fuzzing
2017-05-10 12:54:24 -07:00
Wesley W. Terpstra
3eaa973da7
tilelink2: add earlyAck to regression
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
3e7bdcbf5e
tilelink2: Fragmenter should ignore error when not valid
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e
tilelink2: keep earlyAck Fragmenter sources distinct
2017-05-09 17:35:22 -07:00
Wesley W. Terpstra
2d8a49cc06
tilelink2: Fragmenter client must request global FIFO
2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1
axi4: Test AXI4-Lite in regression
2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845
axi4: SRAM support 0 userBits
2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86
axi4: Deinterleaver must gather R also for single ID
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In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2
axi4: IdIndexer; a single ID does NOT imply no response interleaving
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Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599
tilelink: ToAXI4 - must interlock till last beat
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AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411
axi4: IdIndexer now handles 0-width IDs
2017-05-08 00:17:02 -07:00
Scott Johnson
1cc665717d
Wes fix for AXI2TL timeout when writes backed up
2017-05-04 00:54:21 -07:00
Henry Cook
1f1240baf1
fuzzer: allow fuzzing range to be overridden
2017-05-03 15:29:14 -07:00