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Commit Graph

295 Commits

Author SHA1 Message Date
5045696f92 TLRational: test all corners
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
2017-02-17 14:44:31 +01:00
924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
e8c8d2af71 Heterogeneous Tiles (#550)
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
83a83c778a Added range function in IdRange
Added source accessor function in TLEdge
2017-02-02 12:35:57 -08:00
e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
f7f52cc722 diplomacy: restore Monitor functionality 2017-01-29 17:25:14 -08:00
972953868c uncore: switch to new diplomacy Node API
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
830d01329d RationalCrossing: add some documentation 2017-01-26 21:27:34 -08:00
fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) 2016-12-15 19:10:53 -08:00
a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
aae9b23036 Update with paratermized LazyModule 2016-12-12 16:16:56 -08:00
762afcd54a Merge remote-tracking branch 'origin/master' into jchang_test 2016-12-09 16:56:49 -08:00
4c3083c181 Remove unnecessary val 2016-12-09 16:44:30 -08:00
51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
54cc071a64 Fix Fragmenter to ensure logical operations must be sent out atomically.
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
020fbe8be9 diplomacy: make config.Parameters available in bundle connect()
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
cff2612cdb minor Changes needed to support formal tests 2016-12-01 15:02:23 -08:00
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00
c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
0097274ea3 Broadcast: single-cycle response is possible 2016-11-22 20:45:40 -08:00
c31b41a7ac [tl2] add grant finisher comment 2016-11-19 19:16:43 -08:00
8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00