riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity
4,732 Commits 1 Branch 0 Tags 13 MiB
Commit Graph

1634 Commits

Author SHA1 Message Date
Andrew Waterman 3e04a99f61 Refactor frontend exception passing 
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
 2017-06-28 02:09:18 -07:00
Andrew Waterman cc2f87c214 Forbid S-mode execution from user memory 
285c81746f
 2017-06-28 02:09:18 -07:00
Andrew Waterman 8aa16a11f3 Reduce D$ access energy when refill width > access width 2017-06-28 02:09:18 -07:00
Andrew Waterman 25f585f2a9 Remove unused signal from TLB interface 2017-06-28 02:09:18 -07:00
Andrew Waterman d5f80df0ae Allow speculative I$ refill to cacheable regions 
Backpedaling on 27b143013f.  Shaving
four cycles off of I$ miss penalty is obviously worth the HW cost.
 2017-06-28 02:09:18 -07:00
Megan Wachs 3fc75c2714 debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. 2017-06-27 17:40:58 -07:00
Megan Wachs e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. 2017-06-27 14:10:13 -07:00
Megan Wachs 136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) 2017-06-27 13:42:38 -07:00
Megan Wachs 3b9550ede3 debug: correctly declare reg_debugint 2017-06-27 13:42:38 -07:00
Megan Wachs 56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) 2017-06-27 13:42:38 -07:00
Megan Wachs 665c2a349c Correct Debug + WFI Interactions 
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
 2017-06-27 13:42:38 -07:00
Zihao Yu c9cfe46604 rocket,Rocket: fix type mismatch (#819) 2017-06-27 11:22:08 -07:00
Wesley W. Terpstra 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Wesley W. Terpstra 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits 
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
 2017-06-23 17:22:45 -07:00
Wesley W. Terpstra feecfb53ed axi4: Deinterleaver need not make a Q for an unused AXI id 2017-06-23 17:22:42 -07:00
Wesley W. Terpstra 9bea7c1c58 Merge pull request #815 from freechipsproject/reduce-others 
Reduce others
 2017-06-23 12:13:48 -07:00
Wesley W. Terpstra 2d8b2f4edd ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
Henry Cook ad4b454b49 isp: passthru based on edgesOut = edgesIn (#814) 2017-06-22 21:23:49 -07:00
Wesley W. Terpstra 48611266fa diplomacy: use ReduceOthers in the RegMapper 2017-06-22 19:43:47 -07:00
Wesley W. Terpstra 11d1cb02eb util ReduceOthers produces nlogn cost ready-valid logic 2017-06-22 19:43:20 -07:00
Jack Koenig 1f137cb9ff Merge pull request #800 from ss2783/patch-1 
GeneratorUtils: support to elaborate a RawModule
 2017-06-22 12:34:41 -07:00
Colin Schmidt aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
 2017-06-22 12:07:09 -07:00
Henry Cook bf431c0a53 groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
Wesley W. Terpstra 2f2fe0a973 clint: don't ask for what you know (nTiles) 2017-06-20 17:21:53 -07:00
Henry Cook 1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names 2017-06-20 17:18:45 -07:00
Henry Cook 5552f23294 tims: explictly name them for generated address map 2017-06-20 17:18:29 -07:00
Henry Cook 6b79842e66 dcache: just left shift by untagbits to get tag 
Always safe because of the requirement on coreplex/RocketTiles.scala:126
 2017-06-20 16:35:28 -07:00
Wesley W. Terpstra bb309e573f TLSplitter: special-case the case of no split necessary 2017-06-20 14:10:25 -07:00
Wesley W. Terpstra 53f030c037 TLSplitter: default policy is roundRobin 
Track commit 274d908d98
 2017-06-20 14:03:01 -07:00
Wesley W. Terpstra 1aa4f5ce33 TLSplitter: QoR improvements 
Track commit 985d9750e6
 2017-06-20 14:01:07 -07:00
Wesley W. Terpstra f6e0dd12c8 TLSplitter: ManagerUnification is not used in Xbars 
Track the change made in 5994714970
 2017-06-20 13:58:30 -07:00
Andrew Waterman f396b4142d Merge pull request #806 from freechipsproject/mulh 
Improve integer mul/div
 2017-06-20 13:01:16 -07:00
Colin Schmidt 675f183dd2 refactor ICache to be reusable by other frontends (#808) 
* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction
 2017-06-20 08:21:01 -07:00
Andrew Waterman a6d9884cc0 Improve integer mul/div 
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
 2017-06-19 12:09:21 -07:00
Richard Xia 61c39da475 Check for rvc before declaring illegal instruction after an ebreak. 2017-06-16 10:49:36 -07:00
Wesley W. Terpstra 93d423d202 diplomacy: optimize IdRange.contains (#798) 
This should make an optimal circuit for a wider class of ranges.
 2017-06-15 15:56:14 -07:00
Shreesha Srinath 4059d9417f GeneratorUtils: support to elaborate a RawModule 2017-06-15 14:33:02 -07:00
Henry Cook 5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Wesley W. Terpstra 1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager 
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
 2017-06-14 14:27:23 -07:00
Wesley W. Terpstra 4a15d47061 diplomacy: BufferParams can now directly create a Queue 2017-06-14 13:47:37 -07:00
Wesley W. Terpstra b4b165112c PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave 
This edge has the largest number of source bits by far. Let's just exclude it.
 2017-06-13 16:59:29 -07:00
Wesley W. Terpstra 94f85e8bc8 tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
Colin Schmidt 8264c0a77e add a debug print for xbar id mappings 2017-06-13 16:58:21 -07:00
Henry Cook 9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook 2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Andrew Waterman 76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman 8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Andrew Waterman 5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman 8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Leway Colin 60c896b48c Typo: is should be if ? (#786) 
Typo: is should be if ?
 2017-06-07 10:40:13 -07:00
Andrew Waterman d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Andrew Waterman 07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Megan Wachs 8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Wesley W. Terpstra 87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Megan Wachs 7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs 8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
solomatnikov 274d908d98 Changed TLXbar arbitration policy to roundRobin (#781) 2017-06-05 10:20:28 -07:00
Andrew Waterman 16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew Waterman 27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew Waterman 0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew Waterman 8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew Waterman 7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew Waterman 84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew Waterman 07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew Waterman 6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Wesley W. Terpstra b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra 81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra 5a2a6b0386 diplomacy: add a CustomNode type that allows direct overload of methods 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra fed1f53afa tilelink2: add a TLSplitter to be used for the ISP port 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra a4bf678954 tilelink2: fix latent Xbar truncation bug 
This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra ce12a64f4b tilelink2: support SplitterNodes 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra de39af7f65 tilelink2: make some Xbar methods reusable 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra 0a2a93c27d diplomacy: add the new Splitter node type 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra c695237050 diplomacy: make :=* and :*= resolution more flexible 2017-06-02 20:42:16 -07:00
edwardcwang cdbf67be68 Add a note to wire up jtag_mfr_id (#778) 
Close #774
 2017-06-02 18:53:14 -07:00
Wesley W. Terpstra e0741a2097 axi4: don't map unused masters into TL source ID space 2017-06-02 16:30:16 -07:00
Wesley W. Terpstra 80c63c0da6 rocket: include hartid in cache master names 2017-06-02 15:52:23 -07:00
Wesley W. Terpstra d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra 475ac93cdf coreplex: print memory map using DTS, also write a JSON for it 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra ae8734da05 diplomacy: report cacheability in ResourceAddress 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra 985d9750e6 tilelink2: Xbar QoR improvement 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra 9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used 2017-06-02 14:27:37 -07:00
Wesley W. Terpstra eb14329c63 tilelink2: only combine managers of the same resources 2017-06-01 15:34:43 -07:00
Wesley W. Terpstra 1f531b1593 tilelink2: improve round robin arbiter QoR 2017-06-01 15:34:40 -07:00
Wesley W. Terpstra 5994714970 diplomacy: move manager unification to meta-data only 
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
 2017-06-01 15:30:20 -07:00
Wesley W. Terpstra 0fe625c52f diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Yunsup Lee 6124bf0cc2 sort entires in the printed address map (#773) 2017-05-31 07:45:46 -10:00
Jacob Chang e3e77d68e6 PTW now does not require atomic memory operations, so take out the requirement (#767) 
Bug fix in CSR which manifest itself when compiling a config with no extension
 2017-05-26 13:11:15 -07:00
Andrew Waterman dbc5e7c494 Add TLB miss performance counters (#762) 2017-05-23 12:52:25 -07:00
Andrew Waterman b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Henry Cook 940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Wesley W. Terpstra 7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) 
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
 2017-05-18 22:49:59 -07:00
Wesley W. Terpstra 748a48f667 unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra bea2489507 unittest: make overall test duration configurable 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra c8ba6b2feb unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra f6f40b1442 unit tests: all should accept timeout override 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra 8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer 2017-05-17 06:47:21 -07:00
Wesley W. Terpstra 1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument 2017-05-17 06:46:07 -07:00
Wesley W. Terpstra f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily 2017-05-17 06:29:03 -07:00