6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
...
* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00
907d369bde
Remove tests obsoleted by new FP encoding proposal ( #672 )
2017-04-11 19:12:35 -07:00
1c36ab8bf7
Fragmenter: forbid multiple sink IDs
...
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
2017-04-11 12:38:00 -07:00
84dc2ae822
CacheCork: remove probe support
2017-04-11 12:34:18 -07:00
9a983c12a3
Implement new FP encoding proposal
...
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-04-10 22:38:25 -07:00
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
71bf929505
maskgen: support wider granularity result ( #665 )
...
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
a43bf2feae
Add vectored interrupt support
...
4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
051acee76c
Debug: Fix off-by-1 for detecting nonexistent harts.
2017-04-07 16:47:16 -07:00
01372e1686
use Wire() correctly to assign a value
2017-04-07 16:47:16 -07:00
9ae4838708
jtag: Get rid of chisel deprecation warnings
2017-04-07 16:47:16 -07:00
22c6f728c3
debug: Use flags for resume instead of program buffer. Untested.
2017-04-07 16:47:16 -07:00
d361e9e343
debug: temporarily leave preexec in place
2017-04-07 16:47:16 -07:00
0e2c34b0d6
debug: update register map with new spec
2017-04-07 16:47:16 -07:00
df5caba7bf
debug: Make it easier to override parts of the Default Debug Config ( #655 )
...
* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
...
This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
2601740542
debug: fix some typos related to the ID->SEL mapping functions
2017-04-05 15:14:32 -07:00
b94f1f15b0
debug: redirect DMI NOPs to CONTROL register so things don't hang during reset
2017-04-05 15:14:32 -07:00
eef05cc1fc
debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes.
2017-04-05 15:14:32 -07:00
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
629e9a2ef6
debug: Put DebugROM back inside the overall Debug Module ( #647 )
2017-04-03 16:36:53 -07:00
d2c1bdc2ce
Debug Controls ( #639 )
...
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
80fb002962
Don't use Vec as lvalue
2017-03-30 00:36:23 -07:00
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
375a039279
debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
2017-03-28 21:14:22 -07:00
ca9a5a1cf7
debug: Fixes in how the SimDTM was hooked up to FESVR
2017-03-28 21:13:45 -07:00
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
...
Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
db3ed12ce3
Fix regression in groundtest DummyPTW
...
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
2017-03-28 00:56:14 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
d6ab929c41
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
42ca597478
debug: Breaking change until FESVR is updated as well.
...
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
0c3d85b52b
debug: add generated ROM contents and register fields.
2017-03-27 21:01:36 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
2017-03-27 16:30:46 -07:00
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
2017-03-27 16:30:46 -07:00
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
11507ac7d6
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
...
This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
bf648514e3
TLROM: allow name and compatibility strings to be provided by subclasses.
2017-03-26 20:58:14 -07:00
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
...
* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00
0e2b780089
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
e710e32f10
Implement new FP encoding proposal
...
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
7180352067
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
bb42f3bf3b
WIP on FPU subword recoding
2017-03-26 14:20:16 -07:00
537274b645
coreplex: move buffers inside the coreplex
...
This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
...
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
f36b1766f8
TLROM: use the smallest ROM implementation that works
...
The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
3f0d2fe826
Instantiate PTW unconditionally
...
This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
e9cadf29d2
Improve DCache MMIO QoR
...
No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
...
This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
d3bda9574c
Put page homogeneity checker in PMP
...
Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
9e05200e51
Don't require that PMP ranges be aligned to access size
...
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
2888779422
Flush pipeline from WB stage, not MEM
...
Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
44ca3b60ab
Retime PTW response valid bits
...
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
2a413e4496
Remove fruitless debug()
2017-03-24 16:39:52 -07:00
29414f3a23
Simplify interrupt-stack discipline
...
f2ed45b179
2017-03-24 16:39:52 -07:00
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
7484f27ed3
Don't gate exception-cause pipeline registers separately
...
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
3ea822c2cf
Make blocking L1 D$ the default
...
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
1b950128e1
PTW should always use S-mode privilege
...
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
b1b405404d
Set PRV=M when entering debug mode
...
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
cf168e419b
Support SFENCE.VMA rs1 argument
...
This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
797c18b8db
Make some requirement failures more verbose ( #608 )
...
* tilelink: verbose requires in xbar
* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
bd08f10816
tilelink2: make sink ids optional ( #607 )
...
* tilelink2: make sink ids optional
* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
19eb9b6906
l1tol2: put a flow Q on the exits ( #606 )
...
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
055b8ba1f0
rocket: avoid LinkedHashMap.keys to preserve traversal order ( #603 )
2017-03-22 14:38:33 -07:00
76f083b469
FIFOFixer: Not all D-channel messages are A-channel responses
2017-03-21 14:17:38 -07:00
3609254e4a
There's no structural hazard on MMIO store responses
...
So don't stall as though there were.
2017-03-21 14:17:32 -07:00
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
4c00066746
rocket: describe dcache as two clients (fifo+cached)
2017-03-21 11:16:51 -07:00
81d717e82f
coreplex: guarantee FIFO for those tiles that need it
2017-03-21 11:16:51 -07:00
198afddb4b
tilelink2: add the FIFOFixer
2017-03-21 11:16:51 -07:00
c33f31dd3c
tilelink2 RAMModel: weaken fifo requirement check
2017-03-21 11:16:51 -07:00
930438adba
tilelink2 SourceShrinker: destroy FIFO behaviour
2017-03-21 11:16:51 -07:00
fd521c56a6
tilelink2: add client-side FIFO parameterization
2017-03-21 11:16:51 -07:00
4eef317e84
RegisterRouter: support devices with gaps
2017-03-20 14:49:22 -07:00
431cb41e27
tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
2017-03-20 14:49:22 -07:00
04892fea01
Monitor: support early ack
2017-03-20 14:49:19 -07:00
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
778e189bba
Monitor: ProbeAckData and ReleaseData may carry an error
2017-03-20 11:44:13 -07:00
48c7aed4e1
Monitor: any probe supported by the client is legal
2017-03-20 11:34:19 -07:00
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
c9459fe4eb
tilelink2 Xbar: don't use unnecessary ports
2017-03-19 17:02:24 -07:00
7971947d6c
tilelink2 Monitor: don't inspect bits if valid is forbidden
2017-03-19 16:34:23 -07:00
a4ca424a22
AHBToTL: finally get the error signal right? ( #594 )
2017-03-18 22:24:20 -07:00
f6daa782d3
AHBToTL: fix the order of updates to d_pause ( #592 )
2017-03-17 19:34:40 -07:00
dcc9827ab4
Rename Prci.scala to Clint.scala ( #591 )
...
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
2017-03-17 15:36:10 -07:00
db55a1d755
Fragmenter: fix a bug when underlying device supports larger bursts ( #589 )
2017-03-17 11:00:49 -07:00
9b5b3279a6
AHBToTL: don't report error during idle cycles
2017-03-16 18:18:29 -07:00
5efd38bf97
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
963d244094
unittest: try both aFlow settings of TLToAHB
2017-03-16 15:13:57 -07:00
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
c95c2ca9c8
AHB: include bridge unit tests
2017-03-14 18:34:21 -07:00
0c5fd76089
ahb: implement a ToTL bridge
2017-03-14 18:34:17 -07:00
7f71df0925
apb: better test coverage
2017-03-14 18:34:17 -07:00
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00
3c5c877409
tilelink2: make TLBuffer API more flexible
2017-03-14 14:06:18 -07:00
6fc3ec3d63
tileink2: add a TestRAM; a zero-delay RAM useful for testing
...
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
2017-03-14 14:06:17 -07:00
bb0390630c
Merge branch 'master' into priv-1.10
2017-03-13 21:40:12 -07:00
1322a02637
Fixed Hasti can't handle N masters to one slave #571 ( #576 )
2017-03-13 20:36:53 -07:00
d6f571cbbb
Implement mstatus.TSR
2017-03-13 14:50:06 -07:00
1fea0460ba
Support superpage entries in TLB
2017-03-13 14:50:06 -07:00
2d267b4940
Support corner cases in TLBPermissions
...
Don't crap out if the yes-set or no-set is empty.
2017-03-13 14:50:06 -07:00
90b5cc96cb
Gracefully handle empty ports in AddressDecoder
2017-03-13 14:50:06 -07:00
c847559853
TLB: add a helper API to determine homogeneous page permissions
2017-03-13 14:50:06 -07:00
eaf474a081
LFSR: use random intial value of the start register
...
We just need to make sure it doesn't initialize randomly stuck at 0.
2017-03-13 13:17:52 -07:00
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
...
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
63f8ce36f6
Avoid VM exceptions in groundtest by setting Accessed bit
2017-03-09 16:48:28 -08:00
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
33b6d48376
Fix haltnot reporting (previously always returned 0)
2017-03-09 13:58:40 -08:00
24a2278fc4
Perform all illegal-instruction detection in ID stage
...
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
74d8d672bf
Improve BTB critical path at slight accuracy cost
...
Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
...
We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
603b8af2eb
Don't canonicalize 32-bit FP results in the various pipelines
...
It's redundant with the new scheme, so just adds HW for no reason.
2017-03-07 20:51:32 -08:00
f505aba1ac
Use sNaN value for flw, like other single-precision ops
2017-03-07 20:51:32 -08:00
cc389bea90
Fix in-register representation of fdiv.s/fsqrt.s result
...
We were zero-extending it, which is a double-precision zero in the recoded
format. So, when spilled and reloaded with fsd/fld, the original value
was destroyed. Instead, set the MSBs so that it represents sNaN. When
spilled, the single-precision number will be preserved as the NaN payload.
2017-03-07 20:51:32 -08:00
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
229fb2251d
coreplex: hack to fix tile dedup ( #569 )
2017-03-06 16:36:03 -08:00
676974281a
rocket: describe dcache scratchpad as memory
2017-03-03 02:54:48 -08:00
1eeaa390c6
diplomacy: output JSON formatted version of DTS
2017-03-03 02:45:11 -08:00
0178248551
diplomacy: evaluate ResourceBindings only once
2017-03-03 02:04:17 -08:00
8e4f348dda
rocket: if no MMU, don't print it in DTS
2017-03-03 00:48:26 -08:00
7660be039c
rocketchip: add WithTimebase to set RTC frequency
2017-03-03 00:47:50 -08:00
57a329408c
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
2017-03-03 00:28:55 -08:00
4535de2669
rocket: use diplomatic interrupts
...
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
d3c5318714
build: remove the now obsolete config string
2017-03-02 21:19:23 -08:00
93ca555c20
IntXing: support configurable sync depth
2017-03-02 21:19:23 -08:00
637bc6c3a7
coreplex: pretty print discontiguous ranges properly
2017-03-02 21:19:23 -08:00
7ff9f88ad7
rocket: connect interrupt map for Plic+Clint
2017-03-02 21:19:22 -08:00
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
5bd9f18e5b
rocket: add dts cpu description
2017-03-02 21:19:22 -08:00
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
9a5e2e038b
uncore: add DTS meta-data for devices
2017-03-02 21:19:22 -08:00
0b950b5938
coreplex: bind assigned resources
2017-03-02 21:19:19 -08:00
7f6a250dbf
tilelink2: add hooks for Resources
2017-03-02 21:19:19 -08:00
e322692d16
diplomacy: add DeviceTree renderer
2017-03-02 21:19:14 -08:00
c01a74f4a0
diplomacy: add AddressRange conversion to/from AddressSet
2017-03-02 11:14:28 -08:00
bb70b1a3c3
diplomacy: add resource tracking
2017-03-02 11:14:28 -08:00
9bfcb40cb4
util: Majority on sets of bools
2017-02-27 20:18:28 -08:00
6958f05a85
Merge remote-tracking branch 'origin/master' into periphery-adjustments
2017-02-27 19:40:55 -08:00
62f5727bc6
periphery: peripheryBusBytes and socBusBytes
2017-02-27 19:19:41 -08:00
dfa61bc487
Standardize Data.holdUnless and SeqMem.readAndHold
...
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
2017-02-25 03:07:49 -08:00
fd972f5c67
icache: back-pressure is unnecessary ( #564 )
...
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
2017-02-24 21:01:56 -08:00
35877e6ec1
Merge branch 'master' into periphery-adjustments
2017-02-24 10:37:41 -08:00
87d909e996
Fix HastiTestSRAM can't R/W byte when HSIZE is 0 ( #563 )
2017-02-24 10:37:26 -08:00
a281ad8ad2
rocketchip: rename some periphery ports
2017-02-23 18:28:04 -08:00
6c3011d513
periphery: make external interrupts a UInt rather than a Vec[Bool]
2017-02-23 18:27:44 -08:00
c01aec9259
tilelink2: support unused IntXing
2017-02-22 18:41:06 -08:00
735e4f8ed6
diplomacy: use HeterogeneousBag instead of Vec
...
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
2017-02-22 17:05:22 -08:00
027d6247b6
diplomacy: silence a warning ( #560 )
2017-02-22 11:28:04 -08:00
9153a9a733
ClockDivider: add docs to appease the reviewer
...
... even though this means a delay of 1:30 hours :(
2017-02-17 19:35:08 +01:00
3931b0faff
coreplex: assume L1 runs no slower than L2
2017-02-17 15:15:41 +01:00
5045696f92
TLRational: test all corners
...
In order to ensure that verilator is happy, we launch both clocks from a
clock divider. Sadly, it does not follow the spec wrt. derived clocks.
See the verilator manual section on "Generated Clocks".
2017-02-17 14:44:31 +01:00
91d1880dbf
ClockDivider2: fix launch alignment of clocks (vcs)
...
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.
See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
2017-02-17 14:26:23 +01:00
924afebbd9
tilelink2: make TLRational have configurable direction
2017-02-17 13:59:54 +01:00
bb334a2cf5
util: add fast2slow direction option to rational crossings
...
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
2017-02-17 13:59:51 +01:00
e51609aec0
build: support waveform debug using opensource tools
...
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.
This patch adds targets:
run-regression-tests-fst
run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
2017-02-17 03:38:17 +01:00
abe344a1a4
tilelink2 Fuzzer: support read-only mode ( #555 )
2017-02-13 00:18:47 +01:00
5fc44bbcda
Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. ( #554 )
2017-02-10 10:19:22 -08:00
e8c8d2af71
Heterogeneous Tiles ( #550 )
...
Fundamental new features:
* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.
Additional changes that got rolled in along the way:
* rocket: Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
307e0ca9c0
Fix up Absolute value.
...
As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt.
2017-02-08 15:00:43 -08:00
69f4c1a144
AddressDecoder: support AddressSets with infinite bits ( #547 )
2017-02-04 15:59:50 -08:00
d1744a5667
coreplex: zero memory channels is also allowed
2017-02-03 19:00:08 -08:00
a3e56cfa5e
rocketchip: add Zero device to the memory subsystem
2017-02-03 17:19:24 -08:00
b240505a15
rocketchip: move memory channel Xbar from coreplex to rocketchip
...
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
2017-02-03 17:19:21 -08:00
fc9ea62d38
HeterogeneousBag: a handy container for differently parameterized bundles
2017-02-03 16:21:33 -08:00
7afe383db3
Ecc: detect uncorrectable errors also for SEC
2017-02-03 16:21:09 -08:00
7aba066e67
tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways
2017-02-03 16:20:27 -08:00
93b2fa197e
Artefact output ( #545 )
...
* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
83a83c778a
Added range function in IdRange
...
Added source accessor function in TLEdge
2017-02-02 12:35:57 -08:00
8225676a86
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
...
See https://github.com/riscv/riscv-isa-sim/issues/76
2017-02-02 11:55:08 -08:00
75edf42323
Set xPIE=1 on xRET
...
We were setting xPIE=0 instead. This is a benign bug, but still a bug.
2017-02-02 11:55:08 -08:00
9ca8f514c0
rocket: creating Bundles in an object also break dedup!
2017-01-31 14:45:11 -08:00
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
dc66c8857f
diplomacy: be more robust using Java introspection
...
If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
2017-01-30 14:25:12 -08:00
280af9684b
BankedL2Config: use the same LazyModule for all L2 banks
...
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
2017-01-30 14:02:59 -08:00
f7f52cc722
diplomacy: restore Monitor functionality
2017-01-29 17:25:14 -08:00
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
4d646939b0
diplomacy: make flexible-port adapters possible
2017-01-29 14:26:02 -08:00
24ee7f45f5
rocketchip: pass variable l1tol2 connections into coreplex
2017-01-29 11:18:36 -08:00
d5fa159063
diplomacy: add :*= and :=* to support flexible # of edges
2017-01-28 21:32:36 -08:00
03f2fe02ac
coreplex: support rational crossing to L2 ( #534 )
2017-01-27 17:09:43 -08:00
830d01329d
RationalCrossing: add some documentation
2017-01-26 21:27:34 -08:00
fc3b72084f
tilelink2: add a rational clock crossing adapter
2017-01-26 20:07:28 -08:00
4b70386393
AsyncCrossing: disambiguate the file name
2017-01-26 20:07:28 -08:00
5cf4b0632d
RationalCrossing: clock crossing between related clock domains
2017-01-26 20:07:28 -08:00
0fe2899c74
[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit ( #528 )
2017-01-25 12:10:49 -08:00
6ff35a387a
tilelink2: disable A=>D bypass in ToAXI4 whenever possible
2017-01-24 18:11:00 -08:00
64e1de751d
axi4: add a minLatency parameter
2017-01-24 18:11:00 -08:00
46cdfc2b45
diplomacy: find names of LazyModules also in Seq() member values ( #527 )
2017-01-24 18:10:37 -08:00
3fc55298ef
coreplex: provide coherence managers with geometry information
2017-01-23 15:50:39 -08:00
d4b3a0f0be
diplomacy: support given bits in AddressDecoder
2017-01-23 15:50:39 -08:00
c0b6d31377
tilelink2: Delayer adapter useful for unit tests
2017-01-23 15:50:39 -08:00
38c9ddffcc
BankedL2: move TLFilter BEFORE coherence manager
...
This lets smart caches exclude the sets that are filtered.
2017-01-21 13:23:07 -08:00
dcadd5a006
coreplex: move TLBuffers for L2 and socBus
2017-01-20 22:23:36 -08:00
9dc7f180b6
diplomacy: support zero-port Nodes
2017-01-19 19:08:01 -08:00
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
3a5e5a65f8
coreplex: support multiple memory channels via diplomatic trickery
2017-01-19 19:07:14 -08:00
e7b35b4bb6
diplomacy: support multiple ports behind a BlindNode
2017-01-19 19:07:14 -08:00
258abc5629
coreplex: re-enable stateless L2 config
2017-01-19 19:07:14 -08:00
4bdb2e5d68
tilelink2 Monitor: ReleaseAck source does not count
2017-01-19 19:07:14 -08:00
fbf1073586
tilelink2: CacheCork - terminate caching
2017-01-19 19:07:14 -08:00
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
e0411c6cde
[coreplex] bugfix: re-enable multicore configs via WithNCores
2017-01-19 17:48:04 -08:00
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
e22b01a6fa
jtag_dtm: Update regression to run and pass.
2017-01-18 12:08:13 -08:00
9a6634cd40
Add TLBuffers on the L1 backends and blind exit points ( #513 )
...
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
52bb6cd9d9
Configs: use a uniform syntax without Match exceptions ( #507 )
...
* Configs: use a uniform syntax without Match exceptions
The old style of specifying Configs used total functions. The only way to
indicate that a key was not matched was to throw an exception. Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup. The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
2017-01-13 14:41:19 -08:00
59eb7c24ee
Add iterator function to LazyModule to iterate over all nodes
2017-01-12 15:21:10 -08:00
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
...
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
c531093898
Fix bug introduced with Fuzzer when nOperations is power of 2 ( #492 )
2016-12-15 19:10:53 -08:00
a9b264e582
ahb: lower hsel when idle to save power
2016-12-15 15:32:30 -08:00
16febe7e94
apb: add a TileLink to APB bridge and unittest it
2016-12-15 15:32:27 -08:00
ed091f55e6
apb: diplomatic APB framework
2016-12-15 13:48:50 -08:00
a5b8fc2317
RegisterRouterTest: start up with 0 in registers to make VIP testing easier
2016-12-14 15:38:08 -08:00
9d50704b64
ahb: don't violate spec with SRAM fuzzing
2016-12-14 15:18:41 -08:00
2dd9e522a0
Merge branch 'master' into jchang_test
2016-12-12 20:02:53 -08:00
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
...
* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
531f3684ed
Removing module list for merging. (will need to create iterator in future)
2016-12-12 16:25:31 -08:00
aae9b23036
Update with paratermized LazyModule
2016-12-12 16:16:56 -08:00
762afcd54a
Merge remote-tracking branch 'origin/master' into jchang_test
2016-12-09 16:56:49 -08:00
4c3083c181
Remove unnecessary val
2016-12-09 16:44:30 -08:00
09afbbafdb
ahb: weaken RegisterRouter assertion
...
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
2016-12-08 18:00:39 -08:00
588b944ed4
ahb: implement and test address decoding
2016-12-08 18:00:39 -08:00
5d1064fcb1
ahb: include a unit test
2016-12-08 18:00:39 -08:00
51dfb9cb06
ahb: TileLink master
2016-12-08 18:00:39 -08:00
01b0f6a52b
ahb: new diplomacy-based AHB bus definition
2016-12-08 18:00:39 -08:00
54cc071a64
Fix Fragmenter to ensure logical operations must be sent out atomically.
...
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
c2eedbfe23
tilelink2 Monitor: use Parameters instead of global variables
2016-12-07 12:24:03 -08:00
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
915697cb09
Fix FEQ flag generation ( #479 )
...
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
fbfa15efea
TLBroadcast: support non-FIFO devices ( #482 )
2016-12-05 22:10:37 -08:00
3c9718ec8f
clint: undefined registers must be zero ( #480 )
...
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
2016-12-05 17:11:53 -08:00
f3d0692619
Make a directory for the config package ( #464 )
...
* [config] make dir structure mirror packages
* [config] expunge max_int
2016-12-05 10:42:16 -08:00
d0a0c887dc
[tracegen] decrease default address bag size ( #462 )
...
while increasing the default number of requests.
2016-12-04 22:46:55 -08:00
36fe024671
CacheName no longer needed in RoCCInterface
...
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
e2ec1d00ad
copyright: normalize /// to // in comments
2016-11-27 22:15:43 -08:00
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
233280e7d2
AsyncBundle: save a wasted bit when depth=1
2016-11-25 18:11:01 -08:00
d755edffcc
DebugTransport: use ToAsyncDebugBus for correct depth
2016-11-25 18:10:28 -08:00
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
...
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
a670f63c81
periphery: a handy trait to turn-off ExtMem
2016-11-23 20:44:45 -08:00
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
566cc9e60b
rocketchip: RTCPeriod config
2016-11-23 20:44:45 -08:00
e87f54d4f7
rocketchip: traits for adding external TL2 ports
2016-11-23 20:44:42 -08:00
4b9dc78951
rocketchip: add a parameter-controlled debug port
2016-11-23 15:35:53 -08:00
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
1e7d597fd3
rocketchip: don't waste too many sources on the AXI master port
2016-11-22 21:48:41 -08:00
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
437be0f36a
PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool))
...
This results in much less Verilog to simulate
2016-11-22 20:39:38 -08:00
f9de7173cc
PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...))
2016-11-22 18:46:11 -08:00
d9a203b0f0
PositionalMultiQueue: convert 'next' to a single write port
2016-11-22 18:38:55 -08:00
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
bbabcf67ff
coreplex: width adapter should happen as part of coherence manager
...
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
a140b07009
rocketchip: cut coreplex from rocketchip
2016-11-22 17:27:58 -08:00
c80ee06472
rocketchip: configString is a lazy property of outer
2016-11-22 17:27:58 -08:00
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
3d644b943c
coreplex: configString is a property of the RISCVPlatform
2016-11-21 21:13:26 -08:00
e8be365b5d
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Andrew Waterman
Yunsup Lee
Jim Lawson
Wesley W. Terpstra
Megan Wachs
solomatnikov
Henry Cook
Andrew Waterman
Leway Colin
Jacob Chang
Jacob Chang
Henry Cook
Schuyler Eldridge