riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,543 Commits 1 Branch 0 Tags 13 MiB
4b86802b1a
Commit Graph

729 Commits

Author SHA1 Message Date
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook
632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Henry Cook
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Wesley W. Terpstra
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Wesley W. Terpstra
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00
Wesley W. Terpstra
cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
Wesley W. Terpstra
1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Wesley W. Terpstra
66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Wesley W. Terpstra
60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Yunsup Lee
2c000a99da compartmentalize Top into periphery traits 2016-09-08 02:08:57 -07:00
Yunsup Lee
e35e7b2ee3 Fix routing in non-contiguous MMIO regions 
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
 2016-09-07 19:28:12 -07:00
Andrew Waterman
7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Colin Schmidt
254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
Andrew Waterman
23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
Andrew Waterman
02a2439222 Support a degenerate PLIC with no interrupts 
Resolves #249
 2016-09-07 11:21:13 -07:00
Andrew Waterman
70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC 
The latter is more the domain of TinyConfig.
 2016-09-07 01:58:25 -07:00
Andrew Waterman
a7f47f3c23 Reduce default BTB size 
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
 2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Yunsup Lee
fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
 2016-09-07 00:05:00 -07:00
Wesley W. Terpstra
d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Yunsup Lee
b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) 
now you can add them in any order.  there's an explicit check at the end to figure out whether there are overlapping regions.
 2016-09-06 21:53:55 -07:00
Wesley W. Terpstra
aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Yunsup Lee
56d81b0034 fix configstring printout with no memory 2016-09-06 10:40:11 -07:00
Wesley W. Terpstra
54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra
3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00
Howard Mao
a7f79aa409 get rid of TileLinkMemorySelector 2016-09-04 10:55:19 -07:00
Howard Mao
f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper 2016-09-04 10:55:19 -07:00
Howard Mao
66de89c4db allow fixed priority routing in Junctions arbiters 2016-09-04 10:55:19 -07:00
Howard Mao
efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types 2016-09-04 10:55:19 -07:00
Howard Mao
b9b79e4fb6 get rid of AtoS RTL 2016-09-04 10:55:19 -07:00
Howard Mao
f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
Yunsup Lee
a4c1942958 flatten Coreplex module hierarchy 2016-09-02 17:45:08 -07:00
Andrew Waterman
63679bb019 Add support for L1 data scratchpads instead of caches 
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
 2016-09-02 16:22:07 -07:00
Jim Lawson
dc9ae19936 Work-around for current Scala compiler "structural type loses implicits". 
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.

    [error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
    [error] possible cause: maybe a semicolon is missing before `value asOutput'?
    [error]   }.asOutput
    [error]     ^
    [error] one error found
    [error] (uncore/compile:compileIncremental) Compilation failed

This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
 2016-09-02 15:38:18 -07:00
Andrew Waterman
fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
Andrew Waterman
e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Andrew Waterman
7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable 2016-09-02 15:27:54 -07:00
Andrew Waterman
6872000f5e Merge pull request #239 from ucb-bar/move_rtc 
Move RTC
 2016-09-02 15:17:49 -07:00
Megan Wachs
af364bc7bc Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal 2016-09-02 15:14:39 -07:00
Megan Wachs
8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications 2016-09-02 11:11:40 -07:00
Andrew Waterman
c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Yunsup Lee
4a7972be31 connect testharness components via member functions (#236) 
to prevent code duplication for new testbenches
 2016-09-01 18:38:39 -07:00
Howard Mao
c66318307c no longer need to set invalidate_lr in RoCC examples 2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c tie off invalidate_lr in RoCC 2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF 2016-08-31 22:00:27 -07:00
Howard Mao
50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4 fix DecoupledTLB to handle misses appropriately 2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
SeungRyeol Lee
b1ce3b8c98 Add address map entries for exported mmio port. 2016-08-31 06:58:38 +09:00
Andrew Waterman
8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
Andrew Waterman
07d48df88a Get rid of FPU RoCC port logic when RoCC not present 
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC.  Thus, when the RoCC was not
present, it was still creating muxes.  Using ex_cp_valid instead
gets rid of them.
 2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
Andrew Waterman
9ca82dd397 reset default MulDiv config to moderately fast default 
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
 2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60 set missing port direction 
Ideally, chisel should flag this as an error.
 2016-08-29 12:31:52 -07:00
Megan Wachs
53ee54dbd1 Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself 2016-08-26 10:40:39 -07:00
Megan Wachs
41aa80c5d7 Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts 2016-08-26 09:32:36 -07:00
Ben Keller
79293f4fa2 Use a better iterator inside the DCache 2016-08-25 20:41:39 -07:00
Henry Cook
115e8edd83 Merge branch 'master' into coreplex_peripheral_interrupts 2016-08-25 17:26:56 -07:00
Henry Cook
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
Megan Wachs
428eed79a1 Allow some External Interrupts to come from Periphery 2016-08-25 14:16:33 -07:00
Megan Wachs
32118269c1 Remove } introduced in merge 2016-08-23 08:20:52 -07:00
Megan Wachs
9974626d6a Merge remote-tracking branch 'origin/master' into HEAD 
Conflicts:
	src/main/scala/rocketchip/TestHarness.scala
 2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44 fix bus axi connections in periphery 2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2 extra devices should get elaborated in a single build function 2016-08-22 11:57:15 -07:00
Scott Johnson
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
mwachs5
22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
Megan Wachs
75efc7dee7 JtagIO's DRV_TDO should be an INPUT 2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb Move files after the file reorganization 2016-08-19 16:11:41 -07:00
Megan Wachs
3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module. 
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0
 2016-08-19 16:08:31 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation 
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
 2016-08-19 16:08:17 -07:00
Howard Mao
f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Andrew Waterman
114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
Andrew Waterman
3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters 
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
 2016-08-19 12:06:17 -07:00
Colin Schmidt
0a6c05a5d8 connect top level interrupts to coreplex 2016-08-18 15:52:44 -07:00
Howard Mao
91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao
1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao
18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao
f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao
d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
David Biancolin
29600f64ec make memsize configurable 2016-08-17 16:31:34 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao
e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao
4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao
0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao
3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Howard Mao
9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao
410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Howard Mao
f04aefc95c get rid of deprecated ZynqAdapter 2016-08-02 13:14:20 -07:00
Howard Mao
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao
b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao
98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Megan Wachs
55c992bb3a Use FoldRight() instead of for loop 2016-08-01 16:56:33 -07:00
Megan Wachs
8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman
058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Howard Mao
cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao
ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao
1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao
75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Megan Wachs
c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Howard Mao
20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Wesley W. Terpstra
9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Howard Mao
e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42 Rename MulDivUnroll to MulUnroll 2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96 Create seperate Mul/Div paramters instead of UseFastMulDiv 2016-07-15 14:40:37 -07:00
Andrew Waterman
ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Howard Mao
90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao
f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao
74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4 make Comparator fit the GroundTest model 2016-06-27 16:01:32 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao
3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
ff43238e6e give DualCoreConfig L2 cache to speed up test runs 2016-06-20 17:58:26 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00