2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
bcaee9834c
travis_wait 30
2017-03-30 13:22:33 -07:00
0828ebe911
debug_v013: bump fesvr to use autoexec feature for memory writes.
2017-03-30 11:46:28 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
c61714a465
Pass MODEL variable to emulator.cc
...
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
2017-03-30 02:08:01 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
9f85b2e996
Do allow make to remove .vpd files on Ctrl-C
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
80fb002962
Don't use Vec as lvalue
2017-03-30 00:36:23 -07:00
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
a14b7b5794
debug_v013: bump riscv-tools for slightly more efficient FESVR
2017-03-29 21:42:36 -07:00
24509fc69f
debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code.
2017-03-29 15:20:07 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
f6e72a3ef6
debug: Bump riscv-tools to pick up FESVR to version that works with debug v013
2017-03-29 14:46:06 -07:00
375a039279
debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
2017-03-28 21:14:22 -07:00
ca9a5a1cf7
debug: Fixes in how the SimDTM was hooked up to FESVR
2017-03-28 21:13:45 -07:00
ff38ebdf5e
debug: Bump FESVR version to initial Debug v13. Doesn't work yet.
2017-03-28 21:12:57 -07:00
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
...
Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
db3ed12ce3
Fix regression in groundtest DummyPTW
...
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
2017-03-28 00:56:14 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
d6ab929c41
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
cbc8d2400a
debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version
2017-03-27 21:24:44 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
42ca597478
debug: Breaking change until FESVR is updated as well.
...
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
0c3d85b52b
debug: add generated ROM contents and register fields.
2017-03-27 21:01:36 -07:00
877e1cfba1
debug: add scripts to generate v13 Debug ROM contents.
2017-03-27 20:51:54 -07:00
ed38787c36
Merge pull request #622 from ucb-bar/priv-1.10
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Various priv-1.10 changes
2017-03-27 19:28:30 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
ab300f7985
Update README_TRAVIS.md
2017-03-27 17:45:50 -07:00
3fc74f3d08
Create README_TRAVIS.md
2017-03-27 17:45:46 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
2017-03-27 16:30:46 -07:00
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
2017-03-27 16:30:46 -07:00
861651587b
debug: Update Makefile to use new OpenOCD and allow for easier debugging. ( #619 )
2017-03-27 15:52:04 -07:00
7014263c29
Update LICENSE.SiFive ( #618 )
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Bump the year for the SiFive license
2017-03-27 14:55:28 -07:00
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
