Megan Wachs
3fc7100048
Merge pull request #917 from freechipsproject/fuzzer_order
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TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 18:39:59 -07:00
Megan Wachs
d9821a74ce
Merge pull request #916 from freechipsproject/transfer_sizes_print
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diplomacy: Pretty Print for TransferSizes
2017-08-02 16:56:36 -07:00
Megan Wachs
595415d207
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
Megan Wachs
fc5c04ed4b
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 14:44:18 -07:00
Megan Wachs
85bdae0fa8
diplomacy: Pretty Print for TransferSizes
2017-08-02 11:40:50 -07:00
Yunsup Lee
f988b91575
Merge pull request #912 from freechipsproject/add-mask-rom
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tilelink: add mask rom
2017-07-31 22:28:11 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Yunsup Lee
4b33249812
Merge pull request #911 from freechipsproject/fix-dcache-bug
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Fix D$ ready-valid signaling bug
2017-07-31 19:14:16 -07:00
Wesley W. Terpstra
42ff74bd34
Merge pull request #910 from freechipsproject/tilelink-map
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Tilelink map
2017-07-31 18:33:09 -07:00
Andrew Waterman
e140893a01
Use 1-entry queue on processor-side E-channel
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The cache can't sink a grant every cycle, so extra E buffering doesn't help.
2017-07-31 18:06:54 -07:00
Andrew Waterman
5681693ccc
Fix a D$ ready-valid signaling regression
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I broke this in 66d06460fa
.
2017-07-31 18:05:14 -07:00
Wesley W. Terpstra
d7fd9d2b82
tilelink: Filter, add another case
2017-07-31 16:51:26 -07:00
Yunsup Lee
71a250b071
Merge pull request #909 from freechipsproject/tile-buffer
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add optional tile boundary buffers
2017-07-31 16:46:22 -07:00
Wesley W. Terpstra
b126105230
tilelink: add TLMap to make it possible to move slaves
2017-07-31 16:39:00 -07:00
Wesley W. Terpstra
13d3ffbcaa
tilelink: Filter now support arbitrary filter functions
2017-07-31 16:38:38 -07:00
Yunsup Lee
7adfd5c431
Merge pull request #906 from freechipsproject/critical-paths
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Mitigate I$->D$->I$ critical path
2017-07-31 16:14:11 -07:00
Megan Wachs
07b4edfc87
Merge pull request #908 from freechipsproject/combo-breaker
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dcache: break potential combinatorial loop
2017-07-31 16:13:01 -07:00
Yunsup Lee
f473e6bad0
tile: add optional boundary buffers
2017-07-31 15:57:22 -07:00
Yunsup Lee
cb3529bbc3
util: tweak rational crossings to avoid mux in source
2017-07-31 15:10:15 -07:00
Henry Cook
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
Andrew Waterman
d811692c3b
Mitigate I$->D$->I$ critical path
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This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
2017-07-31 01:43:04 -07:00
Yunsup Lee
ea1840c4b1
Merge pull request #904 from freechipsproject/fix-dcache-bug
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Fix D$ ready-valid signaling bug
2017-07-29 20:30:47 -07:00
Andrew Waterman
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
Andrew Waterman
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
Wesley W. Terpstra
8e2e931770
Merge pull request #903 from freechipsproject/monitor-probes
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tilelink: use the Monitor to enforce Probe sourcing
2017-07-29 01:12:08 -07:00
Wesley W. Terpstra
56e28026a6
TLError: does not need to be fast; cut the loop
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The SystemBus already has a flow buffer on outputs.
2017-07-29 00:22:21 -07:00
Wesley W. Terpstra
540256e24a
systembus: all slaves should have an output buffer
2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
eadf4e9fcc
Revert "tile: add option for tile boundary buffers"
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This reverts commit b64b87ad07
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The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
2017-07-29 00:03:24 -07:00
Wesley W. Terpstra
68064ba260
systembus: don't double down on buffers
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The order should be:
master => buffer|xing => fifofixer => splitter => xbar
2017-07-29 00:02:12 -07:00
Yunsup Lee
140086e2c5
Merge pull request #902 from freechipsproject/perf-improvements
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Perf improvements
2017-07-28 20:12:10 -07:00
Wesley W. Terpstra
a0db929003
tilelink: use the Monitor to enforce Probe sourcing
2017-07-28 18:08:00 -07:00
Megan Wachs
573890e102
Merge pull request #900 from freechipsproject/more_verbose_requires
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diplomacy: More verbose require
2017-07-28 13:23:33 -07:00
Andrew Waterman
fdb8935712
Improve fidelity of two perf counters
2017-07-28 13:14:04 -07:00
Andrew Waterman
4c82f6b77e
Don't refill BTB on not-taken branches
2017-07-28 13:13:52 -07:00
Andrew Waterman
2e8b02e780
Merge D$ store hits when ECC is enabled
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This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
Andrew Waterman
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
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The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
Andrew Waterman
ae1f7a95f6
Don't nack misses when there's a pending store
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That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
Henry Cook
7eeb9dfd88
Merge pull request #899 from freechipsproject/wrapper-dedup
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Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Megan Wachs
f61fe2be1e
diplomacy: More verbose require
2017-07-28 10:05:45 -07:00
Wesley W. Terpstra
370cc392e0
Merge pull request #898 from freechipsproject/uncached-acquire
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tilelink: it is now legal to support Acquire for UNCACHED regions
2017-07-27 22:14:53 -07:00
Wesley W. Terpstra
5f81c2243f
tilelink: add BusBypass, useful to turn devices off
2017-07-27 20:16:30 -07:00
Wesley W. Terpstra
9a36755b6a
tilelink: CacheCork uses constructor helpers
2017-07-27 18:38:15 -07:00
Wesley W. Terpstra
45189c3e30
tilelink: CacheCork now supports errors and BtoT upgrade
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- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
2017-07-27 18:38:13 -07:00
Wesley W. Terpstra
2e4f1611ed
tilelink: Error device supports Acquire
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We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Henry Cook
b64b87ad07
tile: add option for tile boundary buffers
2017-07-27 17:30:51 -07:00
Henry Cook
289ef30dbc
coreplex: change AsynchronousCrossing.sync default to 3
2017-07-27 15:44:51 -07:00
Henry Cook
266ed56e8d
tile: turn off more slave port monitors
2017-07-27 15:28:53 -07:00
Henry Cook
9a483af6e8
coreplex: naming of tile wrappers
2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965
coreplex: remove superfluous sink and source from wrapper
2017-07-27 14:23:03 -07:00
Wesley W. Terpstra
651da73d89
tilelink: it is now legal to support Acquire for UNCACHED regions
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These cases exist:
GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
UNCACHED && !supportsAcquire: speculation ok and may be cached
UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
CACHED, TRACKED && supportsAcquire: slave might probe
2017-07-27 11:11:22 -07:00