Andrew Waterman and GitHub
e21b74c232
Merge pull request #724 from ucb-bar/rvc-speculative
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Fix RVC/uncacheable instruction memory performance bug
2017-05-03 18:48:49 -07:00
Andrew Waterman and Yunsup Lee
4efcb5a139
Increase frontend decoupling ( #722 )
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Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
Andrew Waterman and Yunsup Lee
d6e69066a5
Fix ITIM loads ( #716 )
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An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman and GitHub
9b688ce7e2
Merge pull request #707 from ucb-bar/itim
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ITIM
2017-04-28 02:55:01 -07:00
Andrew Waterman and Wesley W. Terpstra
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
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Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
Andrew Waterman and Henry Cook
915697cb09
Fix FEQ flag generation ( #479 )
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FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
Andrew Waterman
a98127c09e
Merge branch 'ss-frontend'
2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3
Merge branch 'master' into ss-frontend
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Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703
More control cleanup
2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11
Flush pipeline from MEM stage
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This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1
Continue refactoring control
2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9
Much refactor, so control
2015-01-03 13:34:38 -08:00
Andrew WatermanandGitHub
