Henry Cook
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407d8e473e
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first cut at parameter-based testing
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2015-07-13 14:54:26 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Schuyler Eldridge
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b4cd8c5981
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Fix vlsi_mem_gen for Python 2 or 3
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2015-06-25 12:48:31 -07:00 |
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Yunsup Lee
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70b0f9fd4d
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error out for PCWM-L, port width mismatch
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2014-09-25 06:50:50 -07:00 |
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Yunsup Lee
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221007595b
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allow BACKEND/CONFIG be environment variables
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2014-09-17 11:12:08 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Yunsup Lee
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275b72368b
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add CONFIG to the name of simulator executable
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2014-09-11 22:11:58 -07:00 |
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Yunsup Lee
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5f8bd18fac
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Makefiles should be perfect
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2014-09-11 02:53:46 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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cfecd8832d
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tease out reference-chip specific stuff
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2014-09-09 20:49:28 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Yunsup Lee
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1cb2d1d7b7
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initialize all SRAMs to avoid X propagation problem
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2014-09-04 11:06:01 -07:00 |
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Yunsup Lee
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763c57931b
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fix problem introduced with verilog generation in vsim/fsim
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2014-09-04 09:49:57 -07:00 |
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Scott Beamer
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6c6f5a3843
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add verilog target to build without simulator
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2014-09-03 17:28:45 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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