riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra
c115913624 tilelink2 Buffer: increase the minLatency on ports 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e tilelink2 Fuzzer: test Atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d tilelink2 RAMModel: support (by ignoring) atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a tilelink2 AtomicAutomata: prototype flow control complete 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa tilelink2: add a general-purpose Arbiter 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8 tilelink2 Fuzzer: only generate legal atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics 
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves 2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b tilelink2 Bundles: add 1-way snoop bundles 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled 2016-09-22 15:14:19 -07:00
Henry Cook
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Wesley W. Terpstra
3f3defb130 Merge pull request #329 from ucb-bar/fragmenter 
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
 2016-09-22 14:42:55 -07:00
Henry Cook
47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Albert Ou
d76b762657 tilelink2 Fragmenter: Mask low bits of D channel addr_lo 
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
 2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Howard Mao
cbd702e48e make sure junctions and uncore unittests both run 2016-09-21 20:17:52 -07:00
mwachs5
9acb352cf6 Correct Merge Conflitct -- clock, not clk (#327) 
I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
 2016-09-21 20:02:01 -07:00
Yunsup Lee
1b1ef3be07 simplify base Coreplex bundle 2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
mwachs5
3a809b209f Allow Makefile override of RESET_DELAY (#322) 2016-09-21 18:28:30 -07:00
Henry Cook
64fe010369 [unittest] Config import tweaks 2016-09-21 17:40:39 -07:00
Henry Cook
fd5e00fed9 [coreplex] rename Testing.scala -> RocketTestSuite.scala 2016-09-21 17:35:39 -07:00
Henry Cook
270011b768 [unittest] more Config cleanup 2016-09-21 17:30:14 -07:00
Colin Schmidt
2522bdd7b8 Merge pull request #321 from ucb-bar/add-multiclock-coreplex 
add multiclock support to Coreplex
 2016-09-21 17:23:34 -07:00
Yunsup Lee
7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Andrew Waterman
8e63f4a1a5 Remove ClockToSignal and vice-versa 
Clock.asUInt and Bool.asClock now suffice.
 2016-09-21 16:17:14 -07:00
Andrew Waterman
2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
Henry Cook
335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Andrew Waterman
12d0c00822 Fix mtime RegField handling 
RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking.  Avoid RegField.bytes by splitting mtime into
a Seq of words.
 2016-09-20 15:00:52 -07:00
Henry Cook
6f6480ad9f Merge pull request #303 from ucb-bar/testharness-refactor 
TestHarness refactoring
 2016-09-20 14:45:05 -07:00
Henry Cook
40f6f31611 [unittest] further refactor unittest framework 2016-09-20 14:14:30 -07:00
Henry Cook
ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
Henry Cook
b97a0947a9 [rocketchip] enable piecewise Generator output 2016-09-20 12:57:56 -07:00
Howard Mao
74fc7c5803 Merge pull request #315 from ucb-bar/fix-addrmap-error-msg 
correctly print out the addrmap overlapping error message
 2016-09-19 19:39:56 -07:00
Yunsup Lee
1a09e46f69 Merge branch 'master' into fix-addrmap-error-msg 2016-09-19 18:08:58 -07:00
Yunsup Lee
15e7041ccb Merge pull request #316 from ucb-bar/dynamic-reset-vector 
Allow reset vector to be set dynamically
 2016-09-19 18:00:25 -07:00
Andrew Waterman
3b38736a8e Make BaseTopModule and BaseTopModule abstract 
They aren't meant to be directly instantiated.
 2016-09-19 17:18:35 -07:00
Andrew Waterman
d0572d6aab Allow reset vector to be set dynamically 
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
 2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd Expose carry-out bits from WideCounter 2016-09-19 15:54:17 -07:00
Henry Cook
2961d92244 [testharness] vsim makefrag cleanup 2016-09-19 15:14:45 -07:00
Yunsup Lee
1b26d78114 correctly print out the addrmap overlapping error message 2016-09-19 13:34:58 -07:00
Henry Cook
df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Henry Cook
7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00
Henry Cook
7ff7076dab Merge pull request #310 from ucb-bar/rxia-testharness-refactor 
Resolve merge conflicts in testharness-refactor
 2016-09-19 10:22:49 -07:00
Andrew Waterman
f0debb89e4 Merge pull request #314 from ucb-bar/widecounter-reset 
Allow WideCounter to not be reset
 2016-09-18 22:37:40 -07:00