Wesley W. Terpstra
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
Henry Cook
6958f05a85
Merge remote-tracking branch 'origin/master' into periphery-adjustments
2017-02-27 19:40:55 -08:00
Andrew Waterman
dfa61bc487
Standardize Data.holdUnless and SeqMem.readAndHold
...
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
735e4f8ed6
diplomacy: use HeterogeneousBag instead of Vec
...
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
2017-02-22 17:05:22 -08:00
Wesley W. Terpstra
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
f7f52cc722
diplomacy: restore Monitor functionality
2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
64e1de751d
axi4: add a minLatency parameter
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
9dc7f180b6
diplomacy: support zero-port Nodes
2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
e7b35b4bb6
diplomacy: support multiple ports behind a BlindNode
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Wesley W. Terpstra
d067e87a7d
tilelink2 Parameters: sinkId is per port, not per manager
2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
015c3b862a
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7
Debug: mark the debug device executable
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
Andrew Waterman
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
Wesley W. Terpstra
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
Wesley W. Terpstra
7c334e3c34
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3
axi4 ToTL: handle bad AXI addresses
2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f
axi4: Test ToTL
2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a
axi4: prototype ToTL adapter
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f
axi4 Bundles: add a size calculation helper
...
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
4c1c52486b
axi4 Fragmenter: handle more inflight AXI requests than we have space
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131
axi4 Fragmenter: refine sideband FSM for case of last fragment
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b
axi4 Fragmenter: align all output accesses
...
We promised the output is aligned. Make good on that!
2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3
axi4 Fragmenter: confirm correct handling of last
2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b
axi4 Fragmenter: initialize error response to 0
2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba
axi4 Fragmenter: optimize dynamic slave lookup
2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c
axi4: add a Buffer to put between nodes
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e
tilelink2 RAMModel: include name of test in output
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b
axi4: include unit tests
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848
axi4: prototype Fragmenter
2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89
axi4: name AdapterNode parameters properly
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844
axi4: parameterized AXI master constraint for aligned access
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
38b6c1c820
tilelink2 axi4: RegisterRouter can cut ready dependency
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32
axi4 tilelink2: include minAlignment and maxAddress in slaves
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
876609eb0e
diplomacy: add NodeHandles to support abstraction
2016-10-10 13:15:25 -07:00
Wesley W. Terpstra
e856cbe3a6
axi4: SRAM for testing
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
abb02aa6f4
axi4: add a RegisterRouter for generic devices
2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
b29d34038e
axi4: diplomacy capable AXI4
2016-10-10 11:21:50 -07:00