Wesley W. Terpstra
|
198afddb4b
|
tilelink2: add the FIFOFixer
|
2017-03-21 11:16:51 -07:00 |
|
Wesley W. Terpstra
|
c33f31dd3c
|
tilelink2 RAMModel: weaken fifo requirement check
|
2017-03-21 11:16:51 -07:00 |
|
Wesley W. Terpstra
|
930438adba
|
tilelink2 SourceShrinker: destroy FIFO behaviour
|
2017-03-21 11:16:51 -07:00 |
|
Wesley W. Terpstra
|
fd521c56a6
|
tilelink2: add client-side FIFO parameterization
|
2017-03-21 11:16:51 -07:00 |
|
Wesley W. Terpstra
|
d4c9c13fb4
|
Merge pull request #600 from ucb-bar/monitor-spec
Update monitor spec
|
2017-03-20 15:23:34 -07:00 |
|
Wesley W. Terpstra
|
4eef317e84
|
RegisterRouter: support devices with gaps
|
2017-03-20 14:49:22 -07:00 |
|
Wesley W. Terpstra
|
431cb41e27
|
tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
|
2017-03-20 14:49:22 -07:00 |
|
Wesley W. Terpstra
|
04892fea01
|
Monitor: support early ack
|
2017-03-20 14:49:19 -07:00 |
|
Wesley W. Terpstra
|
278f6fea24
|
tilelink2: define is{Request,Response} based on spec
|
2017-03-20 13:41:02 -07:00 |
|
Wesley W. Terpstra
|
778e189bba
|
Monitor: ProbeAckData and ReleaseData may carry an error
|
2017-03-20 11:44:13 -07:00 |
|
Wesley W. Terpstra
|
48c7aed4e1
|
Monitor: any probe supported by the client is legal
|
2017-03-20 11:34:19 -07:00 |
|
Wesley W. Terpstra
|
5a50acfd9d
|
Merge pull request #595 from ucb-bar/ignore-tl-c
Ignore TL-C
|
2017-03-19 18:49:11 -07:00 |
|
Wesley W. Terpstra
|
0c92283a61
|
rocket icache: tie off b ready
|
2017-03-19 17:18:50 -07:00 |
|
Wesley W. Terpstra
|
c9459fe4eb
|
tilelink2 Xbar: don't use unnecessary ports
|
2017-03-19 17:02:24 -07:00 |
|
Wesley W. Terpstra
|
7971947d6c
|
tilelink2 Monitor: don't inspect bits if valid is forbidden
|
2017-03-19 16:34:23 -07:00 |
|
Wesley W. Terpstra
|
a4ca424a22
|
AHBToTL: finally get the error signal right? (#594)
|
2017-03-18 22:24:20 -07:00 |
|
Wesley W. Terpstra
|
d4272db067
|
travis: only run 4 jobs at once (#593)
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
|
2017-03-18 04:14:50 -07:00 |
|
Wesley W. Terpstra
|
f6daa782d3
|
AHBToTL: fix the order of updates to d_pause (#592)
|
2017-03-17 19:34:40 -07:00 |
|
Megan Wachs
|
dcc9827ab4
|
Rename Prci.scala to Clint.scala (#591)
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
|
2017-03-17 15:36:10 -07:00 |
|
Wesley W. Terpstra
|
db55a1d755
|
Fragmenter: fix a bug when underlying device supports larger bursts (#589)
|
2017-03-17 11:00:49 -07:00 |
|
Wesley W. Terpstra
|
eb953c40f0
|
Merge pull request #587 from ucb-bar/ahb-fix
ahb: rewrote TLToAHB to avoid retracting requests on stall
|
2017-03-16 20:55:39 -07:00 |
|
Wesley W. Terpstra
|
9b5b3279a6
|
AHBToTL: don't report error during idle cycles
|
2017-03-16 18:18:29 -07:00 |
|
Wesley W. Terpstra
|
5efd38bf97
|
apb: put both aFlow options under regression
|
2017-03-16 15:36:14 -07:00 |
|
Wesley W. Terpstra
|
882a7ff8ff
|
TLToAPB: use the now standard aFlow parameter name
|
2017-03-16 15:34:59 -07:00 |
|
Wesley W. Terpstra
|
e31b84af33
|
axi4: use common BufferParams
|
2017-03-16 15:32:17 -07:00 |
|
Wesley W. Terpstra
|
ca2c709d29
|
TLBuffer: move TLBufferParams to diplomacy.BufferParams
|
2017-03-16 15:19:36 -07:00 |
|
Wesley W. Terpstra
|
778c8a5c97
|
ToAHB: appease AHB VIP
|
2017-03-16 15:17:05 -07:00 |
|
Wesley W. Terpstra
|
963d244094
|
unittest: try both aFlow settings of TLToAHB
|
2017-03-16 15:13:57 -07:00 |
|
Wesley W. Terpstra
|
604a164b97
|
TLToAHB: rename parameter to aFlow
|
2017-03-16 15:10:54 -07:00 |
|
Wesley W. Terpstra
|
bb49575368
|
ahb: rewrote TLToAHB to avoid retracting requests on stall
|
2017-03-16 14:36:30 -07:00 |
|
Henry Cook
|
4f5f686c7e
|
bump riscv-tools (#586)
|
2017-03-15 18:09:26 -07:00 |
|
Wesley W. Terpstra
|
625919722c
|
Merge pull request #584 from ucb-bar/ahb-in
AHB master port support
|
2017-03-14 19:28:09 -07:00 |
|
Wesley W. Terpstra
|
c95c2ca9c8
|
AHB: include bridge unit tests
|
2017-03-14 18:34:21 -07:00 |
|
Wesley W. Terpstra
|
0c5fd76089
|
ahb: implement a ToTL bridge
|
2017-03-14 18:34:17 -07:00 |
|
Wesley W. Terpstra
|
7f71df0925
|
apb: better test coverage
|
2017-03-14 18:34:17 -07:00 |
|
Wesley W. Terpstra
|
5885bf29b5
|
axi4: improve test harness
|
2017-03-14 18:34:17 -07:00 |
|
Wesley W. Terpstra
|
d98fd942f1
|
tilelink2: optimize the supportsX check circuits
|
2017-03-14 18:34:17 -07:00 |
|
Wesley W. Terpstra
|
3c5c877409
|
tilelink2: make TLBuffer API more flexible
|
2017-03-14 14:06:18 -07:00 |
|
Wesley W. Terpstra
|
6fc3ec3d63
|
tileink2: add a TestRAM; a zero-delay RAM useful for testing
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
|
2017-03-14 14:06:17 -07:00 |
|
Henry Cook
|
e9c694522b
|
Merge pull request #578 from ucb-bar/priv-1.10
Privileged architecture updates
|
2017-03-14 13:20:19 -07:00 |
|
Henry Cook
|
bb0390630c
|
Merge branch 'master' into priv-1.10
|
2017-03-13 21:40:12 -07:00 |
|
Leway Colin
|
1322a02637
|
Fixed Hasti can't handle N masters to one slave #571 (#576)
|
2017-03-13 20:36:53 -07:00 |
|
Henry Cook
|
4eb261c895
|
Merge pull request #582 from ucb-bar/more-fuzzing
Fuzzer enhancements
|
2017-03-13 15:31:51 -07:00 |
|
Andrew Waterman
|
d6f571cbbb
|
Implement mstatus.TSR
|
2017-03-13 14:50:06 -07:00 |
|
Andrew Waterman
|
1fea0460ba
|
Support superpage entries in TLB
|
2017-03-13 14:50:06 -07:00 |
|
Andrew Waterman
|
2d267b4940
|
Support corner cases in TLBPermissions
Don't crap out if the yes-set or no-set is empty.
|
2017-03-13 14:50:06 -07:00 |
|
Andrew Waterman
|
90b5cc96cb
|
Gracefully handle empty ports in AddressDecoder
|
2017-03-13 14:50:06 -07:00 |
|
Wesley W. Terpstra
|
c847559853
|
TLB: add a helper API to determine homogeneous page permissions
|
2017-03-13 14:50:06 -07:00 |
|
Wesley W. Terpstra
|
eaf474a081
|
LFSR: use random intial value of the start register
We just need to make sure it doesn't initialize randomly stuck at 0.
|
2017-03-13 13:17:52 -07:00 |
|
Henry Cook
|
fe287864ef
|
bump firrtl
|
2017-03-13 13:14:16 -07:00 |
|