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Author	SHA1	Message	Date
Stephen Twigg	158cee08af	Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)	2013-09-22 03:18:06 -07:00
Stephen Twigg	cfbfa6b895	Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.	2013-09-05 19:22:34 -07:00
Stephen Twigg	d896ccbd43	Merge branch 'master' into chisel-v2 ... Conflicts: src/main/scala/htif.scala	2013-09-05 16:11:53 -07:00
Stephen Twigg	3132db4f90	Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.	2013-07-30 16:36:28 -07:00