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Commit Graph

4959 Commits

Author SHA1 Message Date
Wesley W. Terpstra
2e4f1611ed tilelink: Error device supports Acquire
We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Henry Cook
b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook
289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 2017-07-27 15:44:51 -07:00
Henry Cook
266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Henry Cook
9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Wesley W. Terpstra
651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions
These cases exist:
  GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
  UNCACHED && !supportsAcquire: speculation ok and may be cached
  UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
  CACHED, TRACKED && supportsAcquire: slave might probe
2017-07-27 11:11:22 -07:00
Wesley W. Terpstra
0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) 2017-07-27 11:07:13 -07:00
Wesley W. Terpstra
9804bdc34e tilelink: remove obsolete addr_lo signal (#895)
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
Wesley W. Terpstra
3cceb866cf Merge pull request #896 from freechipsproject/fuzzer-rage
Fuzzer rage
2017-07-26 16:01:07 -07:00
Wesley W. Terpstra
d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse
The new fuzzer already found it's first victim.
2017-07-26 12:52:29 -07:00
Wesley W. Terpstra
6550ae2e31 tilelink: increase Fuzzer source reuse aggression 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
1efdca106c tilelink: RAMModel support early reuse of source 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
138276fd87 tilelink: SourceShrinker should work also for 0 latency 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
f02c921d0f Merge pull request #893 from freechipsproject/width-update
Width widget enhancements
2017-07-26 12:35:51 -07:00
Wesley W. Terpstra
b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo 2017-07-26 10:31:09 -07:00
Wesley W. Terpstra
ede87c1f73 tilelink: rewrite WidthWidget beat splitter
- split the data based on the address, not the mask
  (the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
2017-07-26 10:24:16 -07:00
Wesley W. Terpstra
0f5065fbf3 tilelink: WidthWidget rewrite beat merging
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
2017-07-26 10:24:12 -07:00
Wesley W. Terpstra
f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894)
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
2017-07-26 10:21:31 -07:00
Andrew Waterman
27d5557177 Merge pull request #891 from freechipsproject/fix-l2-tlb
Fix L2 TLB
2017-07-26 09:43:16 -07:00
Andrew Waterman
5a5b78b15e Improve L2 TLB coding style 2017-07-26 02:22:43 -07:00
Andrew Waterman
5a9c673f41 Fix L2 TLB response bug
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
2017-07-26 02:20:41 -07:00
Andrew Waterman
acca0fccf5 Fix BTB not being refilled on some indirect jumps
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) 2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend
Acquire before release; jump in frontend
2017-07-25 16:26:47 -07:00
Wesley W. Terpstra
c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888)
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.

However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.

To solve this, we alternate an a.source bit every time D completes a txn.
2017-07-25 16:23:55 -07:00
Andrew Waterman
15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Andrew Waterman
62c4080585 Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Andrew Waterman
66d06460fa Add option for acquire-before-release 2017-07-25 15:19:16 -07:00
Andrew Waterman
86ccd935fc Add method to print perf events 2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea Add L2 TLB miss counter 2017-07-25 15:19:16 -07:00
Andrew Waterman
3ced04b70a Mix in trait to connect global_reset_vector 2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668 coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887) 2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a fix HasRTCModuleImp (#885) 2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) 2017-07-21 21:55:32 -07:00
Yunsup Lee
cf75c2049d Merge pull request #878 from freechipsproject/fix-fifofixer
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 20:22:16 -07:00
Yunsup Lee
21954c1c73 tileink: FIFOFixer should cope with zero-latency devices 2017-07-19 19:38:27 -07:00
Howard Mao
4d784ad693 add cloneType to RegisterWriteIO and RegisterReadIO (#874) 2017-07-18 18:52:31 -07:00
Wesley W. Terpstra
8d793daf9c Merge pull request #876 from freechipsproject/sq-helper
ShiftQueue: support constant propagation
2017-07-18 16:30:23 -07:00
Wesley W. Terpstra
a9c58e9d9f diplomacy: support creating ShiftQueues as well 2017-07-18 14:57:02 -07:00
Wesley W. Terpstra
c0a3bb58e9 ShiftQueue: use Vec of Bool to support constant prop of enq.valid 2017-07-18 14:56:59 -07:00
Colin Schmidt
6d0821f19a Update readme to reflect config name changes (#871)
also update list of files expected to be seen in generated-src
2017-07-18 07:27:03 -07:00
Wesley W. Terpstra
416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) 2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
d09a985729 zero: fix attachment in multichannel case (#870) 2017-07-17 21:48:31 -07:00
Wesley W. Terpstra
fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) 2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784 fix the TLFuzzer IO (#869) 2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) 2017-07-14 16:13:30 -07:00
Richard Xia
9ade7af013 Merge pull request #862 from freechipsproject/plic-max-pri-dts
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 17:08:21 -07:00