Commit Graph
32 Commits
Author SHA1 Message Date
Stephen Twigg d2a3b1dc20 Merge branch 'shapeanalysis' 2014-05-06 16:49:54 -07:00
Stephen Twigg cac04afc25 Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL. 2014-04-08 22:14:16 -07:00
Stephen Twigg f643d38672 Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required) 2014-04-08 16:50:52 -07:00
Stephen Twigg 755293d785 Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). 2014-02-14 10:12:09 -08:00
Stephen Twigg 6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
Stephen Twigg 8c96e27ca6 Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
2014-02-04 17:20:28 -08:00
Stephen Twigg 8062888fb9 Push hwacha, rocket, chisel to newest versions 2014-01-28 22:15:41 -08:00
Stephen Twigg e7ee94bcc8 Merge branch 'master' into hwacha-port 2014-01-21 15:23:05 -08:00
Stephen Twigg ee0c4ca291 Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) 2014-01-21 14:48:04 -08:00
Stephen Twigg 3eafbbd1e2 Push hwacha, rocket. All physical tests pass. 2013-11-19 22:16:27 -08:00
Stephen Twigg d7c6824c51 Push riscv-tests and riscv-tools 2013-11-18 13:30:02 -08:00
Stephen Twigg e50c5180cd Merge branch 'master' into hwacha 2013-11-14 16:03:55 -08:00
Stephen Twigg 36e715a797 Use newer version of hwacha (still not quite working but no longer stalls) 2013-11-14 15:56:51 -08:00
Stephen Twigg a870f51300 Add some vector tests 2013-11-14 15:56:25 -08:00
Stephen Twigg 3cdfde9861 Push hwacha, rocket 2013-11-05 15:31:59 -08:00
Stephen Twigg 7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
Stephen Twigg 437f7ed4af Push hardfloat (ignore target files) 2013-09-26 20:51:19 -07:00
Stephen Twigg f6d7e22c46 Push rocket (fix issue with uppermost bit of D$ req tag getting lost) 2013-09-25 11:52:01 -07:00
Stephen Twigg 36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Stephen Twigg eb7e6f03b3 push rocket (AccumulatorExample fixes and documentation) 2013-09-24 16:33:32 -07:00
Stephen Twigg 472b947fbe push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory) 2013-09-24 16:16:12 -07:00
Stephen Twigg eb03f61058 Properly ignore target files. Push uncore (properly ignore target files) 2013-09-24 16:03:28 -07:00
Stephen Twigg 081fcc4e63 push rocket (accelerator interface fixes) 2013-09-24 10:55:22 -07:00
Stephen Twigg fba0ae0fec Push rocket 2013-09-23 00:26:27 -07:00
Stephen Twigg 324a6321bd Push tools (improve consistency: these tools will compile/test the new ISA encoding) 2013-09-22 03:24:11 -07:00
Stephen Twigg 2676ea8279 Push rocket (fix some issues with RoCC although some remain) 2013-09-22 03:19:43 -07:00
Stephen Twigg 6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Stephen Twigg f27c0fb010 Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2 2013-09-05 15:01:56 -07:00
Stephen Twigg 69daae0dae Add dependency resolvers to build.scala to fix build script 2013-09-05 14:56:41 -07:00
Stephen Twigg c1b1a21a0f If +stats is set when running simv-debug, will only output vcd data when cr28 is high. 2013-07-30 16:39:47 -07:00
Stephen Twigg 3f874342a4 Update chisel to appropriate version for reference chip build. 2013-07-10 17:08:56 -07:00
Stephen Twigg bd43ca8423 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-05-23 17:51:24 -07:00