Palmer Dabbelt
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c9a2b7d109
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Add torture as part of the regression
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
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2016-01-31 23:06:59 -08:00 |
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Howard Mao
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55581195eb
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add groundtest submodule for simple memory testing
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2015-11-11 14:33:02 -08:00 |
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Henry Cook
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47bc193c16
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added CDE library as submodule
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2015-10-21 18:24:16 -07:00 |
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Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
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Yunsup Lee
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09e29e8fe0
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add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
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2015-07-07 20:38:47 -07:00 |
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Yunsup Lee
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5ca7f08226
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change rocket submodule
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2014-10-07 03:19:48 -07:00 |
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Yunsup Lee
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e1b8f69cb5
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change submodule pointers to https
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2014-10-07 03:16:20 -07:00 |
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Scott Beamer
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06bc6a45db
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move fpga repo to git@ from https
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2014-10-06 13:45:09 -07:00 |
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Yunsup Lee
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6c18cd9559
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add new fpga-zynq as submodule
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2014-09-30 09:32:02 -07:00 |
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Yunsup Lee
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3175a40509
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add berkeley-hardfloat as submodule
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2014-09-08 00:18:49 -07:00 |
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Yunsup Lee
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1e5b2f658f
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remove existing hardfloat repository
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2014-09-07 23:45:47 -07:00 |
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Henry Cook
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9b36162b67
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Point rocket/ to rocket-staging repo
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2014-08-19 14:20:15 -07:00 |
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Henry Cook
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fc9c676fc1
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add chisel and hardfloat back as sub-projects, bump other sub-projects
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2013-09-26 12:01:46 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Yunsup Lee
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5b55cc93af
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add submodule riscv-tools
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2013-05-10 11:53:55 -07:00 |
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Miquel Moreto
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5d75ddc553
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Added dramsim2 memory model to the emulator backend
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2012-10-14 14:06:28 -07:00 |
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Huy Vo
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084a0d31c3
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initial commit, all the relevant submodules
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2012-09-26 17:46:17 -07:00 |
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