diplomacy: provide a val name for all LazyModule constructions

src/main/scala/tilelink/AsyncCrossing.scala

@@ -78,12 +78,20 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
 
 object TLAsyncCrossingSource
 {
-  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSource(sync)).node
+  def apply(sync: Int = 3)(implicit p: Parameters) =
+  {
+    val asource = LazyModule(new TLAsyncCrossingSource(sync))
+    asource.node
+  }
 }
 
 object TLAsyncCrossingSink
 {
-  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSink(depth, sync)).node
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) =
+  {
+    val asink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    asink.node
+  }
 }
 
 @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
@@ -131,5 +139,6 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAsyncCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/AtomicAutomata.scala

@@ -266,7 +266,10 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 object TLAtomicAutomata
 {
   def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-    LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)).node
+  {
+    val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
+    atomics.node
+  }
 
   case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
 
@@ -318,5 +321,6 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
 }
 
 class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAtomicAutomata(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/Broadcast.scala

@@ -208,7 +208,10 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
 object TLBroadcast
 {
   def apply(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLBroadcast(lineBytes, numTrackers, bufferless)).node
+  {
+    val broadcast = LazyModule(new TLBroadcast(lineBytes, numTrackers, bufferless))
+    broadcast.node
+  }
 }
 
 class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferless: Boolean, edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module

src/main/scala/tilelink/Buffer.scala

@@ -64,7 +64,11 @@ object TLBuffer
       b: BufferParams,
       c: BufferParams,
       d: BufferParams,
-      e: BufferParams)(implicit p: Parameters): TLNode = LazyModule(new TLBuffer(a, b, c, d, e)).node
+      e: BufferParams)(implicit p: Parameters): TLNode =
+  {
+    val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
+    buffer.node
+  }
 
   def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
     val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }

src/main/scala/tilelink/CacheCork.scala

@@ -121,5 +121,9 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
 
 object TLCacheCork
 {
-  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode = LazyModule(new TLCacheCork(unsafe)).node
+  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode =
+  {
+    val cork = LazyModule(new TLCacheCork(unsafe))
+    cork.node
+  }
 }

src/main/scala/tilelink/Delayer.scala

@@ -72,5 +72,9 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object TLDelayer
 {
-  def apply(q: Double)(implicit p: Parameters): TLNode = LazyModule(new TLDelayer(q)).node
+  def apply(q: Double)(implicit p: Parameters): TLNode =
+  {
+    val delayer = LazyModule(new TLDelayer(q))
+    delayer.node
+  }
 }

src/main/scala/tilelink/ErrorEvaluator.scala

@@ -62,5 +62,8 @@ class TLErrorEvaluator(test: RequestPattern, testOn: Boolean, testOff: Boolean)(
 object TLErrorEvaluator
 {
   def apply(test: RequestPattern, testOn: Boolean = false, testOff: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLErrorEvaluator(test, testOn, testOff)).node
+  {
+    val errors = LazyModule(new TLErrorEvaluator(test, testOn, testOff))
+    errors.node
+  }
 }

src/main/scala/tilelink/FIFOFixer.scala

@@ -113,5 +113,9 @@ object TLFIFOFixer
   val allFIFO:        Policy = m => m.fifoId.isDefined
   val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
 
-  def apply(policy: Policy = all)(implicit p: Parameters): TLNode = LazyModule(new TLFIFOFixer(policy)).node
+  def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
+  {
+    val fixer = LazyModule(new TLFIFOFixer(policy))
+    fixer.node
+  }
 }

src/main/scala/tilelink/Filter.scala

@@ -91,5 +91,9 @@ object TLFilter
   def apply(
     Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
     Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
-    )(implicit p: Parameters): TLNode = LazyModule(new TLFilter(Mfilter, Cfilter)).node
+    )(implicit p: Parameters): TLNode =
+  {
+    val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
+    filter.node
+  }
 }

src/main/scala/tilelink/Fragmenter.scala

@@ -294,7 +294,10 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
 object TLFragmenter
 {
   def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None)(implicit p: Parameters): TLNode =
-    LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck)).node
+  {
+    val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
+    fragmenter.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -324,5 +327,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
 }
 
 class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/Fuzzer.scala

@@ -233,7 +233,10 @@ object TLFuzzer
     noModify: Boolean = false,
     overrideAddress: Option[AddressSet] = None,
     nOrdered: Option[Int] = None)(implicit p: Parameters): TLOutwardNode =
-    LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered)).node
+  {
+    val fuzzer = LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered))
+    fuzzer.node
+  }
 }
 
 /** Synthesizeable integration test */

src/main/scala/tilelink/HintHandler.scala

@@ -92,7 +92,10 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 object TLHintHandler
 {
   def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-    LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)).node
+  {
+    val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
+    hints.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -119,5 +122,6 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRAMHintHandlerTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMHintHandler(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMHintHandler(txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/Map.scala

@@ -38,5 +38,9 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
 
 object TLMap
 {
-  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode = LazyModule(new TLMap(fn)).node
+  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode =
+  {
+    val map = LazyModule(new TLMap(fn))
+    map.node
+  }
 }

src/main/scala/tilelink/NodeNumberer.scala

@@ -55,5 +55,9 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
 
 object TLNodeNumberer
 {
-  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode = LazyModule(new TLNodeNumberer(nodeAddressOffset)).node
+  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode =
+  {
+    val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
+    numberer.node
+  }
 }

src/main/scala/tilelink/PatternPusher.scala

@@ -88,5 +88,8 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
 object TLPatternPusher
 {
   def apply(name: String, pattern: Seq[Pattern])(implicit p: Parameters): TLOutwardNode =
-    LazyModule(new TLPatternPusher(name, pattern)).node
+  {
+    val pusher = LazyModule(new TLPatternPusher(name, pattern))
+    pusher.node
+  }
 }

src/main/scala/tilelink/RAMModel.scala

@@ -334,7 +334,10 @@ class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p:
 object TLRAMModel
 {
   def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLRAMModel(log, ignoreErrorData)).node
+  {
+    val model = LazyModule(new TLRAMModel(log, ignoreErrorData))
+    model.node
+  }
 
   case class MonitorParameters(addressBits: Int, sizeBits: Int)
 

src/main/scala/tilelink/RationalCrossing.scala

@@ -78,12 +78,20 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
 
 object TLRationalCrossingSource
 {
-  def apply()(implicit p: Parameters) = LazyModule(new TLRationalCrossingSource).node
+  def apply()(implicit p: Parameters) =
+  {
+    val rsource = LazyModule(new TLRationalCrossingSource)
+    rsource.node
+  }
 }
 
 object TLRationalCrossingSink
 {
-  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) = LazyModule(new TLRationalCrossingSink(direction)).node
+  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) =
+  {
+    val rsink = LazyModule(new TLRationalCrossingSink(direction))
+    rsink.node
+  }
 }
 
 @deprecated("TLRationalCrossing is fragile. Use TLRationalCrossingSource and TLRationalCrossingSink", "rocket-chip 1.2")
@@ -189,5 +197,6 @@ class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModul
 }
 
 class TLRAMRationalCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMRationalCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMRationalCrossing(txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/RegisterRouterTest.scala

@@ -268,7 +268,8 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRR0Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest0(txns)).module).io.finished
+  val dut = Module(LazyModule(new FuzzRRTest0(txns)).module)
+  io.finished := dut.io.finished
 }
 
 class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
@@ -283,6 +284,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRR1Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest1(txns)).module).io.finished
+  val dut = Module(LazyModule(new FuzzRRTest1(txns)).module)
+  io.finished := dut.io.finished
 }
 

src/main/scala/tilelink/SRAM.scala

@@ -90,7 +90,10 @@ object TLRAM
     beatBytes: Int = 4,
     devName: Option[String] = None,
     errors: Seq[AddressSet] = Nil)(implicit p: Parameters): TLInwardNode =
-    LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors)).node
+  {
+    val ram = LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors))
+    ram.node
+  }
 }
 
 /** Synthesizeable unit testing */
@@ -109,5 +112,6 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
 }
 
 class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/SourceShrinker.scala

@@ -74,5 +74,9 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
 
 object TLSourceShrinker
 {
-  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode = LazyModule(new TLSourceShrinker(maxInFlight)).node
+  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode =
+  {
+    val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
+    shrinker.node
+  }
 }

src/main/scala/tilelink/ToAHB.scala

@@ -186,5 +186,9 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
 
 object TLToAHB
 {
-  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAHB(aFlow)).node
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) =
+  {
+    val tl2ahb = LazyModule(new TLToAHB(aFlow))
+    tl2ahb.node
+  }
 }

src/main/scala/tilelink/ToAPB.scala

@@ -85,5 +85,9 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
 
 object TLToAPB
 {
-  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAPB(aFlow)).node
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) =
+  {
+    val tl2apb = LazyModule(new TLToAPB(aFlow))
+    tl2apb.node
+  }
 }

src/main/scala/tilelink/ToAXI4.scala

@@ -227,7 +227,10 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
 object TLToAXI4
 {
   def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
-    LazyModule(new TLToAXI4(combinational, adapterName, stripBits)).node
+  {
+    val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
+    tl2axi4.node
+  }
 
   def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
     if ( a.supportsProbe && !b.supportsProbe) return false

src/main/scala/tilelink/WidthWidget.scala

@@ -184,7 +184,11 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
 
 object TLWidthWidget
 {
-  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = LazyModule(new TLWidthWidget(innerBeatBytes)).node
+  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
+  {
+    val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
+    widget.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -210,5 +214,6 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
 }
 
 class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/tilelink/Xbar.scala

@@ -205,7 +205,10 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
 object TLXbar
 {
   def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters): TLNode =
-    LazyModule(new TLXbar(policy)).node
+  {
+    val xbar = LazyModule(new TLXbar(policy))
+    xbar.node
+  }
 
   def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)).map(_.get)
   def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
@@ -267,7 +270,8 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
 }
 
 class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
+  io.finished := dut.io.finished
 }
 
 class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
@@ -290,5 +294,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
 }
 
 class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
+  val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
+  io.finished := dut.io.finished
 }