96 lines
2.8 KiB
Scala
96 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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trait Pattern {
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def address: BigInt
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def size: Int
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def bits(edge: TLEdgeOut): (Bool, TLBundleA)
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def dataIn: Option[BigInt] = None
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require ((address & ((BigInt(1) << size) - 1)) == 0)
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}
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case class WritePattern(address: BigInt, size: Int, data: BigInt) extends Pattern
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{
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require (log2Floor(data) < (BigInt(8) << size))
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def bits(edge: TLEdgeOut) = edge.Put(UInt(0), UInt(address), UInt(size), UInt(data))
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}
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case class ReadPattern(address: BigInt, size: Int) extends Pattern
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{
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def bits(edge: TLEdgeOut) = edge.Get(UInt(0), UInt(address), UInt(size))
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}
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case class ReadExpectPattern(address: BigInt, size: Int, data: BigInt) extends Pattern
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{
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def bits(edge: TLEdgeOut) = edge.Get(UInt(0), UInt(address), UInt(size))
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override def dataIn = Some(data)
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}
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class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameters) extends LazyModule
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{
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val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(name = name)))))
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val run = Bool(INPUT)
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val done = Bool(OUTPUT)
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})
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val (tl_out, edgeOut) = node.out(0)
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pattern.foreach { p =>
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require (p.size <= log2Ceil(edgeOut.manager.beatBytes), "Patterns must fit in a single beat")
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}
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val step = RegInit(UInt(0, width = log2Ceil(pattern.size+1)))
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val flight = RegInit(Bool(false))
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val ready = RegNext(Bool(true), Bool(false))
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val end = step === UInt(pattern.size)
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io.done := end && !flight
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val a = tl_out.a
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val d = tl_out.d
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// Expected response?
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val check = Vec(pattern.map(p => Bool(p.dataIn.isDefined)))(step) holdUnless a.fire()
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val expect = Vec(pattern.map(p => UInt(p.dataIn.getOrElse(BigInt(0)))))(step) holdUnless a.fire()
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assert (!check || !d.fire() || expect === d.bits.data)
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when (a.fire()) {
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flight := Bool(true)
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step := step + UInt(1)
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}
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when (d.fire()) {
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flight := Bool(false)
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}
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val (plegal, pbits) = pattern.map(_.bits(edgeOut)).unzip
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assert (end || Vec(plegal)(step), s"Pattern pusher ${name} tried to push an illegal request")
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a.valid := io.run && ready && !end && !flight
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a.bits := Vec(pbits)(step)
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d.ready := Bool(true)
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// Tie off unused channels
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tl_out.b.ready := Bool(true)
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tl_out.c.valid := Bool(false)
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tl_out.e.valid := Bool(false)
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}
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}
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object TLPatternPusher
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{
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def apply(name: String, pattern: Seq[Pattern])(implicit p: Parameters): TLOutwardNode =
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{
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val pusher = LazyModule(new TLPatternPusher(name, pattern))
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pusher.node
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}
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}
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