333 lines
15 KiB
Scala
333 lines
15 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import scala.math.{min,max}
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object EarlyAck {
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sealed trait T
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case object AllPuts extends T
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case object PutFulls extends T
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case object None extends T
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}
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// minSize: minimum size of transfers supported by all outward managers
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// maxSize: maximum size of transfers supported after the Fragmenter is applied
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// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
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// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
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// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
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// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
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class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None)(implicit p: Parameters) extends LazyModule
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{
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require (isPow2 (maxSize))
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require (isPow2 (minSize))
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require (minSize < maxSize)
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val fragmentBits = log2Ceil(maxSize / minSize)
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val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
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val toggleBits = 1
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val addedBits = fragmentBits + toggleBits + fullBits
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def expandTransfer(x: TransferSizes) = if (!x) x else {
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// validate that we can apply the fragmenter correctly
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require (x.max >= minSize, s"max transfer size (${x.max}) must be >= min transfer size (${minSize})")
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TransferSizes(x.min, maxSize)
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}
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def shrinkTransfer(x: TransferSizes) =
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if (!alwaysMin) x else
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if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else
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TransferSizes.none
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def mapManager(m: TLManagerParameters) = m.copy(
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supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
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supportsLogical = shrinkTransfer(m.supportsLogical),
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supportsGet = expandTransfer(m.supportsGet),
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supportsPutFull = expandTransfer(m.supportsPutFull),
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supportsPutPartial = expandTransfer(m.supportsPutPartial),
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supportsHint = expandTransfer(m.supportsHint))
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val node = TLAdapterNode(
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// We require that all the responses are mutually FIFO
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// Thus we need to compact all of the masters into one big master
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clientFn = { c => c.copy(clients = Seq(TLClientParameters(
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name = "TLFragmenter",
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sourceId = IdRange(0, c.endSourceId << addedBits),
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requestFifo = true))) },
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managerFn = { m => m.copy(managers = m.managers.map(mapManager)) })
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// All managers must share a common FIFO domain (responses might end up interleaved)
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val manager = edgeOut.manager
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val managers = manager.managers
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val beatBytes = manager.beatBytes
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val fifoId = managers(0).fifoId
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require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
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require (manager.endSinkId <= 1)
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require (minSize >= beatBytes, s"We don't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
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// We can't support devices which are cached on both sides of us
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require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
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/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
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* max size -- the maximum transfer size possible
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* orig size -- the original pre-fragmenter size
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* frag size -- the modified post-fragmenter size
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* min size -- the threshold below which frag=orig
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* beat size -- the amount transfered on any given beat
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*
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* The relationships are as follows:
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* max >= orig >= frag
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* max > min >= beat
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* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
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*
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* The fragment# (sent via TL.source) is measured in multiples of min size.
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* Meanwhile, to track the progress, counters measure in multiples of beat size.
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*
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* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
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*
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* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
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* get64 get16 6 ackD16 6 ackD64 12 15
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* ackD16 6 ackD64 14
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* ackD16 6 ackD64 13
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* ackD16 6 ackD64 12
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* get16 4 ackD16 4 ackD64 8 11
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* ackD16 4 ackD64 10
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* ackD16 4 ackD64 9
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* ackD16 4 ackD64 8
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* get16 2 ackD16 2 ackD64 4 7
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* ackD16 2 ackD64 6
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* ackD16 2 ackD64 5
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* ackD16 2 ackD64 4
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* get16 0 ackD16 0 ackD64 0 3
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* ackD16 0 ackD64 2
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* ackD16 0 ackD64 1
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* ackD16 0 ackD64 0
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*
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* get8 get8 0 ackD8 0 ackD8 0 1
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* ackD8 0 ackD8 0
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*
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* get4 get4 0 ackD4 0 ackD4 0 0
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* get1 get1 0 ackD1 0 ackD1 0 0
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*
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* put64 put16 6 15
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* put64 put16 6 14
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* put64 put16 6 13
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* put64 put16 6 ack16 6 12 12
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* put64 put16 4 11
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* put64 put16 4 10
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* put64 put16 4 9
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* put64 put16 4 ack16 4 8 8
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* put64 put16 2 7
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* put64 put16 2 6
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* put64 put16 2 5
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* put64 put16 2 ack16 2 4 4
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* put64 put16 0 3
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* put64 put16 0 2
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* put64 put16 0 1
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* put64 put16 0 ack16 0 ack64 0 0
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*
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* put8 put8 0 1
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* put8 put8 0 ack8 0 ack8 0 0
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*
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* put4 put4 0 ack4 0 ack4 0 0
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* put1 put1 0 ack1 0 ack1 0 0
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*/
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val counterBits = log2Up(maxSize/beatBytes)
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val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
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// Consider the following waveform for two 4-beat bursts:
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// ---A----A------------
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// -------D-----DDD-DDDD
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// Under TL rules, the second A can use the same source as the first A,
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// because the source is released for reuse on the first response beat.
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//
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// However, if we fragment the requests, it looks like this:
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// ---3210-3210---------
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// -------3-----210-3210
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// ... now we've broken the rules because 210 are twice inflight.
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//
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// This phenomenon means we can have essentially 2*maxSize/minSize-1
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// fragmented transactions in flight per original transaction source.
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//
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// To keep the source unique, we encode the beat counter in the low
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// bits of the source. To solve the overlap, we use a toggle bit.
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// Whatever toggle bit the D is reassembling, A will use the opposite.
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// First, handle the return path
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val acknum = RegInit(UInt(0, width = counterBits))
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val dOrig = Reg(UInt())
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val dToggle = RegInit(Bool(false))
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val dFragnum = out.d.bits.source(fragmentBits-1, 0)
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val dFirst = acknum === UInt(0)
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val dLast = dFragnum === UInt(0) // only for AccessAck (!Data)
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val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
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val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
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val dHasData = edgeOut.hasData(out.d.bits)
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// calculate new acknum
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val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
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val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
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assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))
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val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, UInt(0))
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val ack_decrement = Mux(dHasData, UInt(1), dsizeOH >> log2Ceil(beatBytes))
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// calculate the original size
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val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
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when (out.d.fire()) {
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acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
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when (dFirst) {
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dOrig := dFirst_size
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dToggle := out.d.bits.source(fragmentBits)
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}
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}
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// Swallow up non-data ack fragments
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val doEarlyAck = earlyAck match {
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case EarlyAck.AllPuts => Bool(true)
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case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
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case EarlyAck.None => Bool(false)
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}
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val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
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out.d.ready := in.d.ready || drop
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in.d.valid := out.d.valid && !drop
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in.d.bits := out.d.bits // pass most stuff unchanged
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in.d.bits.source := out.d.bits.source >> addedBits
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in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
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// The specification requires that error transition LOW=>HIGH only once per burst.
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// Since we fragmented a big burst into mulitple little bursts, we need to OR them.
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val r_error = Reg(Bool())
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val d_error = (!dFirst && r_error) || out.d.bits.error
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when (out.d.fire()) { r_error := d_error }
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in.d.bits.error := d_error
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// If you do early Ack, errors may not be dropped
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assert (!out.d.valid || !doEarlyAck || !drop || out.d.bits.error === r_error, "Slave device error behaviour unsuitable for earlyAck setting")
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// What maximum transfer sizes do downstream devices support?
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val maxArithmetics = managers.map(_.supportsArithmetic.max)
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val maxLogicals = managers.map(_.supportsLogical.max)
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val maxGets = managers.map(_.supportsGet.max)
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val maxPutFulls = managers.map(_.supportsPutFull.max)
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val maxPutPartials = managers.map(_.supportsPutPartial.max)
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val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
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// We assume that the request is valid => size 0 is impossible
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val lgMinSize = UInt(log2Ceil(minSize))
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val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// Make the request repeatable
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val repeater = Module(new Repeater(in.a.bits))
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repeater.io.enq <> in.a
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val in_a = repeater.io.deq
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// If this is infront of a single manager, these become constants
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val find = manager.findFast(edgeIn.address(in_a.bits))
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val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
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val maxLgLogical = Mux1H(find, maxLgLogicals)
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val maxLgGet = Mux1H(find, maxLgGets)
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val maxLgPutFull = Mux1H(find, maxLgPutFulls)
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val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
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val maxLgHint = Mux1H(find, maxLgHints)
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val limit = if (alwaysMin) lgMinSize else
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MuxLookup(in_a.bits.opcode, lgMinSize, Array(
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TLMessages.PutFullData -> maxLgPutFull,
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TLMessages.PutPartialData -> maxLgPutPartial,
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TLMessages.ArithmeticData -> maxLgArithmetic,
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TLMessages.LogicalData -> maxLgLogical,
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TLMessages.Get -> maxLgGet,
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TLMessages.Hint -> maxLgHint))
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val aOrig = in_a.bits.size
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val aFrag = Mux(aOrig > limit, limit, aOrig)
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val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
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val aHasData = edgeIn.hasData(in_a.bits)
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val aMask = Mux(aHasData, UInt(0), aFragOH1)
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val gennum = RegInit(UInt(0, width = counterBits))
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val aFirst = gennum === UInt(0)
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val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - UInt(1))
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val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
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val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
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val aLast = aFragnum === UInt(0)
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val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
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val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
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when (out.a.fire()) { gennum := new_gennum }
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repeater.io.repeat := !aHasData && aFragnum =/= UInt(0)
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out.a <> in_a
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out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | UInt(minSize-1))
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out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
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out.a.bits.size := aFrag
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// Optimize away some of the Repeater's registers
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assert (!repeater.io.full || !aHasData)
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out.a.bits.data := in.a.bits.data
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val fullMask = UInt((BigInt(1) << beatBytes) - 1)
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assert (!repeater.io.full || in_a.bits.mask === fullMask)
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out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLFragmenter
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{
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def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None)(implicit p: Parameters): TLNode =
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{
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val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
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fragmenter.node
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}
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}
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("Fragmenter"))
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
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(ram.node
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:= TLDelayer(0.1)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.1)
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:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
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:= TLDelayer(0.1)
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:= TLBuffer(BufferParams.flow)
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:= TLFragmenter(ramBeatBytes, maxSize/2)
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:= TLDelayer(0.1)
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:= TLBuffer(BufferParams.flow)
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:= model.node
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:= fuzz.node)
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
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io.finished := dut.io.finished
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}
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