270 lines
9.2 KiB
Scala
270 lines
9.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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class IDMapGenerator(numIds: Int) extends Module {
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val w = log2Up(numIds)
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val io = new Bundle {
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val free = Decoupled(UInt(width = w)).flip
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val alloc = Decoupled(UInt(width = w))
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}
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io.free.ready := Bool(true)
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// True indicates that the id is available
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val bitmap = RegInit(UInt((BigInt(1) << numIds) - 1, width = numIds))
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val select = ~(leftOR(bitmap) << 1) & bitmap
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io.alloc.bits := OHToUInt(select)
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io.alloc.valid := bitmap.orR()
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val clr = Wire(init = UInt(0, width = numIds))
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when (io.alloc.fire()) { clr := UIntToOH(io.alloc.bits) }
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val set = Wire(init = UInt(0, width = numIds))
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when (io.free.fire()) { set := UIntToOH(io.free.bits) }
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bitmap := (bitmap & ~clr) | set
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assert (!io.free.valid || !(bitmap & ~clr)(io.free.bits)) // No double freeing
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}
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object LFSR64
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{
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def apply(increment: Bool = Bool(true)): UInt =
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{
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val wide = 64
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val lfsr = Reg(UInt(width = wide)) // random initial value based on simulation seed
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val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4)
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when (increment) {
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lfsr := Mux(lfsr === UInt(0), UInt(1), Cat(xor, lfsr(wide-1,1)))
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}
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lfsr
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}
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}
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trait HasNoiseMakerIO
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{
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val io = new Bundle {
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val inc = Bool(INPUT)
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val random = UInt(OUTPUT)
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}
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}
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class LFSRNoiseMaker(wide: Int) extends Module with HasNoiseMakerIO
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{
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val lfsrs = Seq.fill((wide+63)/64) { LFSR64(io.inc) }
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io.random := Cat(lfsrs)(wide-1,0)
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}
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object LFSRNoiseMaker {
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def apply(wide: Int, increment: Bool = Bool(true)): UInt = {
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val nm = Module(new LFSRNoiseMaker(wide))
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nm.io.inc := increment
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nm.io.random
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}
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}
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/** TLFuzzer drives test traffic over TL2 links. It generates a sequence of randomized
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* requests, and issues legal ones into the DUT. TODO: Currently the fuzzer only generates
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* memory operations, not permissions transfers.
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* @param nOperations is the total number of operations that the fuzzer must complete for the test to pass
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* @param inFlight is the number of operations that can be in-flight to the DUT concurrently
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* @param noiseMaker is a function that supplies a random UInt of a given width every time inc is true
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*/
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class TLFuzzer(
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nOperations: Int,
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inFlight: Int = 32,
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noiseMaker: (Int, Bool, Int) => UInt = {
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(wide: Int, increment: Bool, abs_values: Int) =>
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LFSRNoiseMaker(wide=wide, increment=increment)
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},
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noModify: Boolean = false,
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overrideAddress: Option[AddressSet] = None,
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nOrdered: Option[Int] = None)(implicit p: Parameters) extends LazyModule
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{
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val clientParams = if (nOrdered.isDefined) {
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val n = nOrdered.get
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require(n > 0, s"nOrdered must be > 0, not $n")
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require((inFlight % n) == 0, s"inFlight (${inFlight}) must be evenly divisible by nOrdered (${nOrdered}).")
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Seq.tabulate(n) {i =>
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TLClientParameters(name =s"OrderedFuzzer$i",
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sourceId = IdRange(i * (inFlight/n), (i + 1)*(inFlight/n)),
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requestFifo = true)
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}
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} else {
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Seq(TLClientParameters(
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name = "Fuzzer",
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sourceId = IdRange(0,inFlight)
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))
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}
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val node = TLClientNode(Seq(TLClientPortParameters(clientParams)))
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val finished = Bool(OUTPUT)
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})
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val (out, edge) = node.out(0)
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// Extract useful parameters from the TL edge
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val maxTransfer = edge.manager.maxTransfer
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val beatBytes = edge.manager.beatBytes
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val maxLgBeats = log2Up(maxTransfer/beatBytes)
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val addressBits = log2Up(overrideAddress.map(_.max).getOrElse(edge.manager.maxAddress))
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val sizeBits = edge.bundle.sizeBits
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val dataBits = edge.bundle.dataBits
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// Progress through operations
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val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations+1)))
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val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations+1)))
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if (nOperations>0) {
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io.finished := num_resps === UInt(0)
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} else {
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io.finished := Bool(false)
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}
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// Progress within each operation
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val a = out.a.bits
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val (a_first, a_last, req_done) = edge.firstlast(out.a)
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val d = out.d.bits
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val (d_first, d_last, resp_done) = edge.firstlast(out.d)
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// Source ID generation
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val idMap = Module(new IDMapGenerator(inFlight))
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val src = idMap.io.alloc.bits holdUnless a_first
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// Increment random number generation for the following subfields
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val inc = Wire(Bool())
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val inc_beat = Wire(Bool())
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val arth_op_3 = noiseMaker(3, inc, 0)
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val arth_op = Mux(arth_op_3 > UInt(4), UInt(4), arth_op_3)
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val log_op = noiseMaker(2, inc, 0)
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val amo_size = UInt(2) + noiseMaker(1, inc, 0) // word or dword
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val size = noiseMaker(sizeBits, inc, 0)
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val rawAddr = noiseMaker(addressBits, inc, 2)
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val addr = overrideAddress.map(_.legalize(rawAddr)).getOrElse(rawAddr) & ~UIntToOH1(size, addressBits)
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val mask = noiseMaker(beatBytes, inc_beat, 2) & edge.mask(addr, size)
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val data = noiseMaker(dataBits, inc_beat, 2)
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// Actually generate specific TL messages when it is legal to do so
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val (glegal, gbits) = edge.Get(src, addr, size)
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val (pflegal, pfbits) = if(edge.manager.anySupportPutFull) {
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edge.Put(src, addr, size, data)
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} else { (glegal, gbits) }
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val (pplegal, ppbits) = if(edge.manager.anySupportPutPartial) {
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edge.Put(src, addr, size, data, mask)
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} else { (glegal, gbits) }
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val (alegal, abits) = if(edge.manager.anySupportArithmetic) {
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edge.Arithmetic(src, addr, size, data, arth_op)
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} else { (glegal, gbits) }
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val (llegal, lbits) = if(edge.manager.anySupportLogical) {
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edge.Logical(src, addr, size, data, log_op)
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} else { (glegal, gbits) }
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val (hlegal, hbits) = if(edge.manager.anySupportHint) {
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edge.Hint(src, addr, size, UInt(0))
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} else { (glegal, gbits) }
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val legal_dest = edge.manager.containsSafe(addr)
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// Pick a specific message to try to send
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val a_type_sel = noiseMaker(3, inc, 0)
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val legal = legal_dest && MuxLookup(a_type_sel, glegal, Seq(
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UInt("b000") -> glegal,
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UInt("b001") -> (pflegal && !Bool(noModify)),
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UInt("b010") -> (pplegal && !Bool(noModify)),
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UInt("b011") -> (alegal && !Bool(noModify)),
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UInt("b100") -> (llegal && !Bool(noModify)),
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UInt("b101") -> hlegal))
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val bits = MuxLookup(a_type_sel, gbits, Seq(
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UInt("b000") -> gbits,
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UInt("b001") -> pfbits,
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UInt("b010") -> ppbits,
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UInt("b011") -> abits,
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UInt("b100") -> lbits,
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UInt("b101") -> hbits))
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// Wire up Fuzzer flow control
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val a_gen = if (nOperations>0) num_reqs =/= UInt(0) else Bool(true)
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out.a.valid := a_gen && legal && (!a_first || idMap.io.alloc.valid)
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idMap.io.alloc.ready := a_gen && legal && a_first && out.a.ready
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idMap.io.free.valid := d_first && out.d.fire()
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idMap.io.free.bits := out.d.bits.source
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out.a.bits := bits
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.d.ready := Bool(true)
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out.e.valid := Bool(false)
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// Increment the various progress-tracking states
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inc := !legal || req_done
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inc_beat := !legal || out.a.fire()
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if (nOperations>0) {
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when (out.a.fire() && a_last) {
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num_reqs := num_reqs - UInt(1)
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}
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when (out.d.fire() && d_last) {
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num_resps := num_resps - UInt(1)
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}
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}
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}
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}
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object TLFuzzer
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{
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def apply(
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nOperations: Int,
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inFlight: Int = 32,
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noiseMaker: (Int, Bool, Int) => UInt = {
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(wide: Int, increment: Bool, abs_values: Int) =>
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LFSRNoiseMaker(wide=wide, increment=increment)
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},
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noModify: Boolean = false,
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overrideAddress: Option[AddressSet] = None,
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nOrdered: Option[Int] = None)(implicit p: Parameters): TLOutwardNode =
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{
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val fuzzer = LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered))
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fuzzer.node
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}
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}
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/** Synthesizeable integration test */
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import freechips.rocketchip.unittest._
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class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
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val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
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val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
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val gpio = LazyModule(new RRTest1(0x400))
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val xbar = LazyModule(new TLXbar)
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val xbar2= LazyModule(new TLXbar)
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val fuzz = LazyModule(new TLFuzzer(txns))
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xbar2.node := TLAtomicAutomata() := model.node := fuzz.node
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ram2.node := TLFragmenter(16, 256) := xbar2.node
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xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node
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ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node
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gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new TLFuzzRAM(txns)).module)
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io.finished := dut.io.finished
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}
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