118 lines
3.9 KiB
Scala
118 lines
3.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.experimental.chiselName
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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class TLRAM(
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address: AddressSet,
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cacheable: Boolean = true,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)
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(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
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{
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(address) ++ errors,
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resources = resources,
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regionType = if (cacheable) RegionType.UNCACHED else RegionType.UNCACHEABLE,
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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minLatency = 1))) // no bypass needed for this device
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lazy val module = new LazyModuleImp(this) {
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val (in, edge) = node.in(0)
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val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
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val a_legal = address.contains(in.a.bits.address)
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val memAddress = Cat(addrBits.reverse)
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val mem = makeSinglePortedByteWriteSeqMem(1 << addrBits.size)
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val d_full = RegInit(Bool(false))
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val d_read = Reg(Bool())
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_data = Wire(UInt())
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val d_legal = Reg(Bool())
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// Flow control
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when (in.d.fire()) { d_full := Bool(false) }
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when (in.a.fire()) { d_full := Bool(true) }
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in.d.valid := d_full
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in.a.ready := in.d.ready || !d_full
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in.d.bits := edge.AccessAck(d_source, d_size, !d_legal)
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// avoid data-bus Mux
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in.d.bits.data := d_data
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in.d.bits.opcode := Mux(d_read, TLMessages.AccessAckData, TLMessages.AccessAck)
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val read = in.a.bits.opcode === TLMessages.Get
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val rdata = Wire(Vec(beatBytes, Bits(width = 8)))
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val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
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d_data := Cat(rdata.reverse)
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when (in.a.fire()) {
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d_read := read
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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d_legal := a_legal
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}
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// exactly this pattern is required to get a RWM memory
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when (in.a.fire() && !read && a_legal) {
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mem.write(memAddress, wdata, in.a.bits.mask.toBools)
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}
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val ren = in.a.fire() && read
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rdata := mem.readAndHold(memAddress, ren)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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object TLRAM
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{
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def apply(
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address: AddressSet,
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cacheable: Boolean = true,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)(implicit p: Parameters): TLInwardNode =
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{
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val ram = LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors))
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ram.node
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}
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}
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/** Synthesizeable unit testing */
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import freechips.rocketchip.unittest._
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class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("SRAMSimple"))
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
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ram.node := TLDelayer(0.25) := model.node := fuzz.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module)
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io.finished := dut.io.finished
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}
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