riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex => subsystem

Browse Source
This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/tilelink/BootROM.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
@ -58,7 +58,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
}
}
/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
trait HasPeripheryBootROM extends HasPeripheryBus {
val dtb: DTB
private val params = p(BootROMParams)
@ -74,7 +74,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
bootrom.node := pbus.toVariableWidthSlaves
}
/** Coreplex will power-on running at 0x10040 (BootROM) */
/** Subsystem will power-on running at 0x10040 (BootROM) */
trait HasPeripheryBootROMModuleImp extends LazyModuleImp
with HasResetVectorWire {
val outer: HasPeripheryBootROM

2
src/main/scala/devices/tilelink/BusBypass.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

20
src/main/scala/devices/tilelink/Clint.scala → src/main/scala/devices/tilelink/CLINT.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -12,7 +12,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import scala.math.{min,max}
object ClintConsts
object CLINTConsts
{
def msipOffset(hart: Int) = hart * msipBytes
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
@ -25,16 +25,16 @@ object ClintConsts
def ints = 2
}
case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
{
def address = AddressSet(baseAddress, ClintConsts.size-1)
def address = AddressSet(baseAddress, CLINTConsts.size-1)
}
case object ClintKey extends Field(ClintParams())
case object CLINTKey extends Field(CLINTParams())
class CoreplexLocalInterrupter(params: ClintParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
import ClintConsts._
import CLINTConsts._
// clint0 => at most 4095 devices
val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
@ -90,8 +90,8 @@ class CoreplexLocalInterrupter(params: ClintParams, beatBytes: Int)(implicit p:
}
}
/** Trait that will connect a Clint to a coreplex */
trait HasPeripheryClint extends HasPeripheryBus {
val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey), pbus.beatBytes))
/** Trait that will connect a CLINT to a subsystem */
trait HasPeripheryCLINT extends HasPeripheryBus {
val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
clint.node := pbus.toVariableWidthSlaves
}

2
src/main/scala/devices/tilelink/Error.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasSystemBus
import freechips.rocketchip.subsystem.HasSystemBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

2
src/main/scala/devices/tilelink/MaskROM.scala
View File

@ -3,7 +3,7 @@
package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.coreplex.{HasPeripheryBus}
import freechips.rocketchip.subsystem.{HasPeripheryBus}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

4
src/main/scala/devices/tilelink/Plic.scala
View File

@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -268,7 +268,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
}
}
/** Trait that will connect a PLIC to a coreplex */
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
plic.node := pbus.toVariableWidthSlaves

2
src/main/scala/devices/tilelink/Zero.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasMemoryBus
import freechips.rocketchip.subsystem.HasMemoryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._