83 lines
2.8 KiB
Scala
83 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import java.nio.{ByteBuffer, ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Size, location and contents of the boot rom. */
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case class BootROMParams(
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address: BigInt = 0x10000,
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size: Int = 0x10000,
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hang: BigInt = 0x10040,
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contentFileName: String)
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case object BootROMParams extends Field[BootROMParams]
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class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
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resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
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{
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(AddressSet(base, size-1)),
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resources = resources,
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regionType = RegionType.UNCACHED,
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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fifoId = Some(0))),
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beatBytes = beatBytes)))
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lazy val module = new LazyModuleImp(this) {
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val contents = contentsDelayed
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val wrapSize = 1 << log2Ceil(contents.size)
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require (wrapSize <= size)
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val (in, edge) = node.in(0)
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val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
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val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
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val rom = Vec(bigs.map(x => UInt(x, width = 8*beatBytes)))
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in.d.valid := in.a.valid
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in.a.ready := in.d.ready
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val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
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val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
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in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, UInt(0), rom(index)))
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
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trait HasPeripheryBootROM extends HasPeripheryBus {
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val dtb: DTB
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private val params = p(BootROMParams)
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private lazy val contents = {
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val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
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val rom = ByteBuffer.wrap(romdata)
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rom.array() ++ dtb.contents
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}
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def resetVector: BigInt = params.hang
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val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
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bootrom.node := pbus.toVariableWidthSlaves
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}
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/** Subsystem will power-on running at 0x10040 (BootROM) */
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trait HasPeripheryBootROMModuleImp extends LazyModuleImp
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with HasResetVectorWire {
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val outer: HasPeripheryBootROM
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global_reset_vector := outer.resetVector.U
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}
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